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temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
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r193:16c5d6a814b5 JC
r594:a9702b7364d2 simu_with_Leon3
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em-LeonLPP-A3PE3kL_testData29.pdc
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set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
set_io data_29 -pinname J18 -fixed yes -DIRECTION Inout
set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
set_io Reset -pinname N18 -fixed yes -DIRECTION Inout