##// END OF EJS Templates
temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

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r482:792dac4c614c JC
r594:a9702b7364d2 simu_with_Leon3
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Makefile.inc
20 lines | 317 B | text/x-povray | MakefileLexer
PACKAGE=\"\"
SPEED=Std
SYNFREQ=50
TECHNOLOGY=ProASIC3E
LIBERO_DIE=IT14X14M4
PART=A3PE3000
DESIGNER_VOLTAGE=COM
DESIGNER_TEMP=COM
DESIGNER_PACKAGE=FBGA
DESIGNER_PINS=324
MANUFACTURER=Actel
MGCTECHNOLOGY=Proasic3
MGCPART=$(PART)
MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
LIBERO_PACKAGE=fg$(DESIGNER_PINS)