##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
jeandet - - Load All Authors

File last commit:

r129:8459a437c1f1 alexis
r594:a9702b7364d2 simu_with_Leon3
Show More
fpga.cmd
7 lines | 143 B | application/x-dos-batch | BatchLexer
/ boards / ICI4-main-BD / fpga.cmd
History | Annotation | Raw |Copy content |Copy permalink
setMode -bs
setCable -port auto
Identify
identifyMPM
assignFile -p 2 -file "xilinx-sp605-xc6slx45t.bit"
Program -p 2 -defaultVersion 0
quit