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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.stdlib.ALL;
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LIBRARY gaisler;
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USE gaisler.libdcom.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.jtagtst.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.data_type_pkg.ALL;
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PACKAGE lpp_sim_pkg IS
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PROCEDURE UART_INIT (
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SIGNAL TX : OUT STD_LOGIC;
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CONSTANT tx_period : IN TIME
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);
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PROCEDURE UART_WRITE_ADDR32 (
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SIGNAL TX : OUT STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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PROCEDURE UART_WRITE (
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SIGNAL TX : OUT STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
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CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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PROCEDURE UART_READ (
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
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DATA : OUT STD_LOGIC_VECTOR
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);
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COMPONENT sig_reader IS
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GENERIC(
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FNAME : STRING := "input.txt";
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WIDTH : INTEGER := 1;
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RESOLUTION : INTEGER := 8;
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GAIN : REAL := 1.0
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);
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PORT(
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clk : IN std_logic;
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end_of_simu : out std_logic;
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out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
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);
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END COMPONENT;
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END lpp_sim_pkg;
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PACKAGE BODY lpp_sim_pkg IS
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PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
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BEGIN
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txc(TX, 16#55#, tx_period);
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END;
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PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
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BEGIN
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txc(TX, 16#c0#, tx_period);
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txa(TX,
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to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
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to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
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to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
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to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
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tx_period);
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txa(TX,
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to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
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to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
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to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
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to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
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tx_period);
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END;
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PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
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CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
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CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
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BEGIN
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txc(TX, 16#c0#, tx_period);
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txa(TX,
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to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
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to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
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to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
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to_integer(UNSIGNED(ADDR_last)),
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tx_period);
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txa(TX,
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to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
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to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
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to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
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to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
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tx_period);
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END;
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PROCEDURE UART_READ (
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
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DATA : OUT STD_LOGIC_VECTOR )
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IS
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VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
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CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
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BEGIN
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txc(TX, 16#80#, tx_period);
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txa(TX,
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to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
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to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
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to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
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to_integer(UNSIGNED(ADDR_last)),
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tx_period);
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rxc(RX,V_DATA,tx_period);
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DATA(31 DOWNTO 24) := V_DATA;
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rxc(RX,V_DATA,tx_period);
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DATA(23 DOWNTO 16) := V_DATA;
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rxc(RX,V_DATA,tx_period);
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DATA(15 DOWNTO 8) := V_DATA;
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rxc(RX,V_DATA,tx_period);
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DATA(7 DOWNTO 0) := V_DATA;
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END;
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END lpp_sim_pkg;
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