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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use lpp.iir_filter.all;
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use work.config.all;
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entity LF_ACQ_TOP is
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generic(
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WordSize : integer := 8;
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WordCnt : integer := 144;
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MinFCount : integer := 64;
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CstDATA : integer := 0;
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IIRFilter : integer := 0
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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SyncSig : in STD_LOGIC;
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minorF : in std_logic;
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majorF : in std_logic;
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sclk : in std_logic;
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WordClk : in std_logic;
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LF_SCK : out std_logic;
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LF_CNV : out std_logic;
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LF_SDO1 : in std_logic;
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LF_SDO2 : in std_logic;
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LF_SDO3 : in std_logic;
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LF1 : out std_logic_vector(15 downto 0);
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LF2 : out std_logic_vector(15 downto 0);
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LF3 : out std_logic_vector(15 downto 0)
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);
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end LF_ACQ_TOP;
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architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is
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signal LF_ADC_SmplClk : std_logic;
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signal LF_ADC_SpPulse : std_logic;
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signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0);
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signal sps : Samples(2 DOWNTO 0);
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signal LFX : Samples(2 DOWNTO 0);
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signal sample_val : std_logic;
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signal AD_in : AD7688_in(2 DOWNTO 0);
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signal AD_out : AD7688_out;
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signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
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signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
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signal sample_out_val : std_logic;
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signal LF1_sync : std_logic_vector(15 downto 0);
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signal LF2_sync : std_logic_vector(15 downto 0);
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signal LF3_sync : std_logic_vector(15 downto 0);
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begin
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AD_in(0).sdi <= LF_SDO1;
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AD_in(1).sdi <= LF_SDO2;
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AD_in(2).sdi <= LF_SDO3;
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LF_SCK <= AD_out.SCK;
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LF_CNV <= AD_out.CNV;
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LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
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generic map(6)
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port map(
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reset => reset,
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wclk => WordClk,
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SMPL_CLK => LF_ADC_SmplClk
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);
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ADC: IF CstDATA =0 GENERATE
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ADCs: AD7688_drvr
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GENERIC map
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(
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ChanelCount => 3,
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clkkHz => 48000
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)
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PORT map
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(
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clk => clk,
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rstn => reset,
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enable => '1',
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smplClk => LF_ADC_SmplClk,
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DataReady => sample_val,
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smpout => sps,
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AD_in => AD_in,
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AD_out => AD_out
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);
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smpPulse: entity work.OneShot
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Port map(
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reset => reset,
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clk => clk,
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input => LF_ADC_SmplClk,
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output => LF_ADC_SpPulse
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);
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NOfilt: IF IIRFilter = 0 GENERATE
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process(reset,clk)
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begin
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if reset ='0' then
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LF1_sync <= (others => '0');
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LF2_sync <= (others => '0');
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LF3_sync <= (others => '0');
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elsif clk'event and clk ='1' then
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if sample_val = '1' then
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LF1_sync <= sps(0);
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LF2_sync <= sps(1);
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LF3_sync <= sps(2);
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end if;
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end if;
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end process;
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END GENERATE;
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filt: IF IIRFilter /= 0 GENERATE
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filtertop: entity work.IIR_FILTER_TOP
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generic map
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(
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V2 => 0
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)
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port map
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(
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rstn => reset,
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clk => clk,
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SMPclk => LF_ADC_SmplClk,
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LF1_IN => sps(0),
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LF2_IN => sps(1),
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LF3_IN => sps(2),
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SMPCLKOut => open,
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LF1_OUT => LF1_sync,
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LF2_OUT => LF2_sync,
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LF3_OUT => LF3_sync
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);
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END GENERATE;
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END GENERATE;
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CST: IF CstDATA /=0 GENERATE
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LF1_sync <= LF1cst;
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LF2_sync <= LF2cst;
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LF3_sync <= LF3cst;
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END GENERATE;
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LF1sync: entity work.Fast2SlowSync
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generic map(N => 16)
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port map( LF1_sync,clk,sclk,SyncSig,LF1);
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LF2sync: entity work.Fast2SlowSync
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generic map(N => 16)
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port map( LF2_sync,clk,sclk,SyncSig,LF2);
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LF3sync: entity work.Fast2SlowSync
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generic map(N => 16)
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port map( LF3_sync,clk,sclk,SyncSig,LF3);
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--Filter: IIR_CEL_FILTER
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-- GENERIC map(
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-- tech => CFG_MEMTECH,
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-- Sample_SZ => Sample_SZ,
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-- ChanelsCount => ChanelsCount,
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-- Coef_SZ => Coef_SZ,
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-- CoefCntPerCel => CoefCntPerCel,
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-- Cels_count => Cels_count,
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-- Mem_use => use_RAM
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-- )
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-- PORT map(
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-- reset => reset,
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-- clk => clk,
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-- sample_clk => LF_ADC_SmplClk,
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-- regs_in : IN in_IIR_CEL_reg;
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-- regs_out : IN out_IIR_CEL_reg;
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-- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
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-- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
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-- GOtest : OUT STD_LOGIC;
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-- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
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--
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-- );
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end AR_LF_ACQ_TOP;
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