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-- ADS1274_DRIVER.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.general_purpose.all;
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entity FAKE_DUAL_ADS1278_DRIVER is
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generic
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(
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SCLKDIV : integer range 2 to 256 :=16
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);
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port(
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Clk : in std_logic;
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reset : in std_logic;
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SpiClk : out std_logic;
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DIN : in std_logic_vector(1 downto 0);
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SmplClk : in std_logic;
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OUT00 : out std_logic_vector(23 downto 0);
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OUT01 : out std_logic_vector(23 downto 0);
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OUT02 : out std_logic_vector(23 downto 0);
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OUT03 : out std_logic_vector(23 downto 0);
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OUT04 : out std_logic_vector(23 downto 0);
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OUT05 : out std_logic_vector(23 downto 0);
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OUT06 : out std_logic_vector(23 downto 0);
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OUT07 : out std_logic_vector(23 downto 0);
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OUT10 : out std_logic_vector(23 downto 0);
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OUT11 : out std_logic_vector(23 downto 0);
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OUT12 : out std_logic_vector(23 downto 0);
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OUT13 : out std_logic_vector(23 downto 0);
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OUT14 : out std_logic_vector(23 downto 0);
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OUT15 : out std_logic_vector(23 downto 0);
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OUT16 : out std_logic_vector(23 downto 0);
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OUT17 : out std_logic_vector(23 downto 0);
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FSynch : out std_logic
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);
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end FAKE_DUAL_ADS1278_DRIVER;
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architecture ar_FAKE_DUAL_ADS1278_DRIVER of FAKE_DUAL_ADS1278_DRIVER is
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signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0);
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signal ShiftGeg20,ShiftGeg21 : std_logic_vector((8*24)-1 downto 0);
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signal SmplClk_Reg : std_logic:= '0';
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signal N : integer range 0 to (24*8) := 0;
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signal SPI_CLk : std_logic;
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signal SmplClk_clkd : std_logic:= '0';
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signal OUT00_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT01_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT02_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT03_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT04_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT05_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT06_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT07_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT10_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT11_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT12_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT13_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT14_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT15_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT16_r : std_logic_vector(23 downto 0) := (others => '0');
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signal OUT17_r : std_logic_vector(23 downto 0) := (others => '0');
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begin
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CLKDIV0 : Clk_Divider2
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generic map(SCLKDIV)
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port map(Clk,SPI_CLk);
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FSynch <= SmplClk;
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SpiClk <= SPI_CLk;
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process(reset,SPI_CLk)
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begin
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if reset = '0' then
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ShiftGeg0 <= (others => '0');
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ShiftGeg1 <= (others => '0');
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N <= 0;
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OUT00_r <= (others => '0');
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OUT01_r <= (others => '0');
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OUT02_r <= (others => '0');
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OUT03_r <= (others => '0');
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OUT04_r <= (others => '0');
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OUT05_r <= (others => '0');
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OUT06_r <= (others => '0');
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OUT07_r <= (others => '0');
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OUT10_r <= (others => '0');
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OUT11_r <= (others => '0');
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OUT12_r <= (others => '0');
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OUT13_r <= (others => '0');
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OUT14_r <= (others => '0');
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OUT15_r <= (others => '0');
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OUT16_r <= (others => '0');
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OUT17_r <= (others => '0');
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ShiftGeg20 <= (others => '0');
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ShiftGeg21 <= (others => '0');
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elsif SPI_CLk'event and SPI_CLk = '1' then
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if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
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ShiftGeg20((8*24)-1 downto 0) <= ShiftGeg20((8*24)-2 downto 0) & '0';
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ShiftGeg21((8*24)-1 downto 0) <= ShiftGeg21((8*24)-2 downto 0) & '0';
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ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & ShiftGeg20((8*24)-1);
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ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & ShiftGeg21((8*24)-1);
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if N = ((24*8)-1) then
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N <= 0;
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OUT00_r <= std_logic_vector(UNSIGNED(OUT00_r) + 1);
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OUT01_r <= std_logic_vector(UNSIGNED(OUT01_r) + 2);
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OUT02_r <= std_logic_vector(UNSIGNED(OUT02_r) + 3);
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OUT03_r <= std_logic_vector(UNSIGNED(OUT03_r) + 4);
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OUT04_r <= std_logic_vector(UNSIGNED(OUT04_r) + 5);
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OUT05_r <= std_logic_vector(UNSIGNED(OUT05_r) + 6);
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OUT06_r <= std_logic_vector(UNSIGNED(OUT06_r) + 7);
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OUT07_r <= std_logic_vector(UNSIGNED(OUT07_r) + 8);
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OUT10_r <= std_logic_vector(UNSIGNED(OUT10_r) + 9);
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OUT11_r <= std_logic_vector(UNSIGNED(OUT11_r) + 10);
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OUT12_r <= std_logic_vector(UNSIGNED(OUT12_r) + 11);
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OUT13_r <= std_logic_vector(UNSIGNED(OUT13_r) + 12);
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OUT14_r <= std_logic_vector(UNSIGNED(OUT14_r) + 13);
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OUT15_r <= std_logic_vector(UNSIGNED(OUT15_r) + 14);
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OUT16_r <= std_logic_vector(UNSIGNED(OUT16_r) + 15);
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OUT17_r <= std_logic_vector(UNSIGNED(OUT17_r) + 16);
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ShiftGeg20((24*1)-1 downto (24*(1-1))) <= OUT00_r;
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ShiftGeg20((24*2)-1 downto (24*(2-1))) <= OUT01_r;
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ShiftGeg20((24*3)-1 downto (24*(3-1))) <= OUT02_r;
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ShiftGeg20((24*4)-1 downto (24*(4-1))) <= OUT03_r;
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ShiftGeg20((24*5)-1 downto (24*(5-1))) <= OUT04_r;
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ShiftGeg20((24*6)-1 downto (24*(6-1))) <= OUT05_r;
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ShiftGeg20((24*7)-1 downto (24*(7-1))) <= OUT06_r;
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ShiftGeg20((24*8)-1 downto (24*(8-1))) <= OUT07_r;
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ShiftGeg21((24*1)-1 downto (24*(1-1))) <= OUT10_r;
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ShiftGeg21((24*2)-1 downto (24*(2-1))) <= OUT11_r;
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ShiftGeg21((24*3)-1 downto (24*(3-1))) <= OUT12_r;
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ShiftGeg21((24*4)-1 downto (24*(4-1))) <= OUT13_r;
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ShiftGeg21((24*5)-1 downto (24*(5-1))) <= OUT14_r;
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ShiftGeg21((24*6)-1 downto (24*(6-1))) <= OUT15_r;
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ShiftGeg21((24*7)-1 downto (24*(7-1))) <= OUT16_r;
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ShiftGeg21((24*8)-1 downto (24*(8-1))) <= OUT17_r;
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else
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N <= N+1;
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end if;
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end if;
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end if;
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end process;
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process(SPI_CLk)
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begin
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if SPI_CLk'event and SPI_CLk ='0' then
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SmplClk_clkd <= SmplClk;
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SmplClk_Reg <= SmplClk_clkd;
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end if;
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end process;
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process(clk,reset)
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begin
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if reset = '0' then
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OUT00 <= (others => '0');
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OUT01 <= (others => '0');
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OUT02 <= (others => '0');
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OUT03 <= (others => '0');
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OUT04 <= (others => '0');
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OUT05 <= (others => '0');
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OUT06 <= (others => '0');
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OUT07 <= (others => '0');
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OUT10 <= (others => '0');
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OUT11 <= (others => '0');
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OUT12 <= (others => '0');
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OUT13 <= (others => '0');
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OUT14 <= (others => '0');
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OUT15 <= (others => '0');
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OUT16 <= (others => '0');
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OUT17 <= (others => '0');
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elsif clk'event and clk ='1' then
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if N = 0 then
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OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1)));
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OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1)));
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OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1)));
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OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1)));
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OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1)));
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OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1)));
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OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1)));
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OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1)));
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OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1)));
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OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1)));
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OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1)));
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OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1)));
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OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1)));
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OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1)));
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OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1)));
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OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1)));
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end if;
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end if;
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end process;
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end ar_FAKE_DUAL_ADS1278_DRIVER;
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