HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/modelsim/gaisler/i2c_slave_model/_primary.vhd

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             _primary.vhd
        
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                VhdlLexer
            
             / designs / Projet-LeonLFR-A3P3K-Sheldon_sim-wfp / modelsim / gaisler / i2c_slave_model / _primary.vhd
          
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      library verilog;

      use verilog.vl_types.all;

      entity i2c_slave_model is

          generic(

              I2C_ADR         : integer := 80;

              idle            : integer := 0;

              slave_ack       : integer := 1;

              get_mem_adr     : integer := 2;

              gma_ack         : integer := 3;

              data            : integer := 4;

              data_ack        : integer := 5

          );

          port(

              scl             : in     vl_logic;

              sda             : inout  vl_logic

          );

      end i2c_slave_model;

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				library verilog;
				use verilog.vl_types.all;
				entity i2c_slave_model is
				generic(
				I2C_ADR : integer := 80;
				idle : integer := 0;
				slave_ack : integer := 1;
				get_mem_adr : integer := 2;
				gma_ack : integer := 3;
				data : integer := 4;
				data_ack : integer := 5
				);
				port(
				scl : in vl_logic;
				sda : inout vl_logic
				);
				end i2c_slave_model;