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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:14:05 07/02/2012
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-- Design Name:
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-- Module Name: lfr_time_management - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.lpp_lfr_time_management.ALL;
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ENTITY lfr_time_management IS
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GENERIC (
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nb_time_code_missing_limit : INTEGER := 60
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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new_timecode : IN STD_LOGIC; -- transition signal information
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new_coarsetime : IN STD_LOGIC; -- transition signal information
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coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fine_time_new : OUT STD_LOGIC;
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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coarse_time_new : OUT STD_LOGIC
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);
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END lfr_time_management;
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ARCHITECTURE Behavioral OF lfr_time_management IS
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SIGNAL counter_clear : STD_LOGIC;
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SIGNAL counter_full : STD_LOGIC;
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SIGNAL nb_time_code_missing : INTEGER;
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SIGNAL coarse_time_s : INTEGER;
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SIGNAL new_coarsetime_s : STD_LOGIC;
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BEGIN
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lpp_counter_1 : lpp_counter
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GENERIC MAP (
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nb_wait_period => 750,
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nb_bit_of_data => 16)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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clear => counter_clear,
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full => counter_full,
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data => fine_time,
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new_data => fine_time_new);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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nb_time_code_missing <= 0;
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counter_clear <= '0';
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coarse_time_s <= 0;
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coarse_time_new <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF new_coarsetime = '1' THEN
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new_coarsetime_s <= '1';
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ELSIF new_timecode = '1' THEN
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new_coarsetime_s <= '0';
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END IF;
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IF new_timecode = '1' THEN
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coarse_time_new <= '1';
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IF new_coarsetime_s = '1' THEN
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coarse_time_s <= to_integer(unsigned(coarsetime_reg));
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ELSE
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coarse_time_s <= coarse_time_s + 1;
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END IF;
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nb_time_code_missing <= 0;
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counter_clear <= '1';
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ELSE
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coarse_time_new <= '0';
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counter_clear <= '0';
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IF counter_full = '1' THEN
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coarse_time_new <= '1';
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coarse_time_s <= coarse_time_s + 1;
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IF nb_time_code_missing = nb_time_code_missing_limit THEN
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nb_time_code_missing <= nb_time_code_missing_limit;
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ELSE
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nb_time_code_missing <= nb_time_code_missing + 1;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
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coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
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END Behavioral;
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