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--
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-- SpaceWire core with character-stream interface.
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--
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-- This entity provides a SpaceWire core with a character-stream interface.
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-- The interface provides means for connection initiation, sending and
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-- receiving of N-Chars and TimeCodes, and error reporting.
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--
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-- This entity instantiates spwlink, spwrecv, spwxmit and one of the
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-- spwrecvfront implementations. It also implements a receive FIFO and
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-- a transmit FIFO.
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--
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-- The SpaceWire standard requires that each transceiver use an initial
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-- signalling rate of 10 Mbit/s. This implies that the system clock frequency
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-- must be a multiple of 10 MHz. See the manual for further details on
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-- bitrates and clocking.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.spwpkg.all;
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entity spwstream is
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generic (
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-- System clock frequency in Hz.
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-- This must be set to the frequency of "clk". It is used to setup
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-- counters for reset timing, disconnect timeout and to transmit
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-- at 10 Mbit/s during the link handshake.
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sysfreq: real;
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-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
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-- This must be set to the frequency of "txclk". It is used to
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-- transmit at 10 Mbit/s during the link handshake.
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txclkfreq: real := 0.0;
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-- Selection of a receiver front-end implementation.
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rximpl: spw_implementation_type := impl_generic;
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-- Maximum number of bits received per system clock
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-- (must be 1 in case of impl_generic).
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rxchunk: integer range 1 to 4 := 1;
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-- Selection of a transmitter implementation.
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tximpl: spw_implementation_type := impl_generic;
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-- Size of the receive FIFO as the 2-logarithm of the number of bytes.
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-- Must be at least 6 (64 bytes).
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rxfifosize_bits: integer range 6 to 14 := 11;
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-- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
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txfifosize_bits: integer range 2 to 14 := 11
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);
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port (
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-- System clock.
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clk: in std_logic;
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-- Receiver sample clock (only for impl_fast)
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rxclk: in std_logic;
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-- Transmit clock (only for impl_fast)
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txclk: in std_logic;
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-- Synchronous reset (active-high).
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rst: in std_logic;
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-- Enables automatic link start on receipt of a NULL character.
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autostart: in std_logic;
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-- Enables link start once the Ready state is reached.
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-- Without autostart or linkstart, the link remains in state Ready.
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linkstart: in std_logic;
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-- Do not start link (overrides linkstart and autostart) and/or
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-- disconnect a running link.
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linkdis: in std_logic;
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-- Scaling factor minus 1, used to scale the transmit base clock into
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-- the transmission bit rate. The system clock (for impl_generic) or
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-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
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-- Changing this signal will immediately change the transmission rate.
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-- During link setup, the transmission rate is always 10 Mbit/s.
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txdivcnt: in std_logic_vector(7 downto 0);
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-- High for one clock cycle to request transmission of a TimeCode.
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-- The request is registered inside the entity until it can be processed.
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tick_in: in std_logic;
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-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
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ctrl_in: in std_logic_vector(1 downto 0);
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-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
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time_in: in std_logic_vector(5 downto 0);
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-- Pulled high by the application to write an N-Char to the transmit
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-- queue. If "txwrite" and "txrdy" are both high on the rising edge
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-- of "clk", a character is added to the transmit queue.
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-- This signal has no effect if "txrdy" is low.
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txwrite: in std_logic;
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-- Control flag to be sent with the next N_Char.
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-- Must be valid while txwrite is high.
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txflag: in std_logic;
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-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
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-- Must be valid while txwrite is high.
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txdata: in std_logic_vector(7 downto 0);
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-- High if the entity is ready to accept an N-Char for transmission.
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txrdy: out std_logic;
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-- High if the transmission queue is at least half full.
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txhalff: out std_logic;
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-- High for one clock cycle if a TimeCode was just received.
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tick_out: out std_logic;
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-- Control bits of the last received TimeCode.
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ctrl_out: out std_logic_vector(1 downto 0);
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-- Counter value of the last received TimeCode.
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time_out: out std_logic_vector(5 downto 0);
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-- High if "rxflag" and "rxdata" contain valid data.
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-- This signal is high unless the receive FIFO is empty.
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rxvalid: out std_logic;
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-- High if the receive FIFO is at least half full.
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rxhalff: out std_logic;
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-- High if the received character is EOP or EEP; low if the received
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-- character is a data byte. Valid if "rxvalid" is high.
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rxflag: out std_logic;
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-- Received byte, or "00000000" for EOP or "00000001" for EEP.
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-- Valid if "rxvalid" is high.
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rxdata: out std_logic_vector(7 downto 0);
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-- Pulled high by the application to accept a received character.
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-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
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-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
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-- and "rxdata" are updated.
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-- This signal has no effect if "rxvalid" is low.
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rxread: in std_logic;
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-- High if the link state machine is currently in the Started state.
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started: out std_logic;
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-- High if the link state machine is currently in the Connecting state.
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connecting: out std_logic;
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-- High if the link state machine is currently in the Run state, indicating
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-- that the link is fully operational. If none of started, connecting or running
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-- is high, the link is in an initial state and the transmitter is not yet enabled.
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running: out std_logic;
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-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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errdisc: out std_logic;
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-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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errpar: out std_logic;
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-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
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-- the link. This indication is auto-clearing.
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erresc: out std_logic;
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-- Credit error detected. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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errcred: out std_logic;
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-- Data In signal from SpaceWire bus.
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spw_di: in std_logic;
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-- Strobe In signal from SpaceWire bus.
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spw_si: in std_logic;
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-- Data Out signal to SpaceWire bus.
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spw_do: out std_logic;
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-- Strobe Out signal to SpaceWire bus.
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spw_so: out std_logic
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);
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end entity spwstream;
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architecture spwstream_arch of spwstream is
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-- Convert boolean to std_logic.
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type bool_to_logic_type is array(boolean) of std_ulogic;
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constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
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-- Reset time (6.4 us) in system clocks
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constant reset_time: integer := integer(sysfreq * 6.4e-6);
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-- Disconnect time (850 ns) in system clocks
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constant disconnect_time: integer := integer(sysfreq * 850.0e-9);
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-- Initial tx clock scaler (10 Mbit).
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type impl_to_real_type is array(spw_implementation_type) of real;
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constant tximpl_to_txclk_freq: impl_to_real_type :=
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(impl_generic => sysfreq, impl_fast => txclkfreq);
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constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
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constant default_divcnt: std_logic_vector(7 downto 0) :=
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std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
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-- Registers.
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type regs_type is record
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-- packet state
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rxpacket: std_logic; -- '1' when receiving a packet
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rxeep: std_logic; -- '1' when rx EEP character pending
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txpacket: std_logic; -- '1' when transmitting a packet
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txdiscard: std_logic; -- '1' when discarding a tx packet
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-- FIFO pointers
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rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
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rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
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txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
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txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
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-- FIFO state
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rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid
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txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid
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rxfull: std_logic; -- '1' if RX fifo is full
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rxhalff: std_logic; -- '1' if RX fifo is at least half full
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txfull: std_logic; -- '1' if TX fifo is full
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txhalff: std_logic; -- '1' if TX fifo is at least half full
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rxroom: std_logic_vector(5 downto 0);
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end record;
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constant regs_reset: regs_type := (
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rxpacket => '0',
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rxeep => '0',
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txpacket => '0',
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txdiscard => '0',
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rxfifo_raddr => (others => '0'),
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rxfifo_waddr => (others => '0'),
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txfifo_raddr => (others => '0'),
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txfifo_waddr => (others => '0'),
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rxfifo_rvalid => '0',
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txfifo_rvalid => '0',
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rxfull => '0',
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rxhalff => '0',
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txfull => '0',
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txhalff => '0',
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rxroom => (others => '0') );
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signal r: regs_type := regs_reset;
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signal rin: regs_type;
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-- Interface signals to components.
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signal recv_rxen: std_logic;
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signal recvo: spw_recv_out_type;
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signal recv_inact: std_logic;
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signal recv_inbvalid: std_logic;
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signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
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signal xmiti: spw_xmit_in_type;
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signal xmito: spw_xmit_out_type;
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signal xmit_divcnt: std_logic_vector(7 downto 0);
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signal linki: spw_link_in_type;
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signal linko: spw_link_out_type;
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-- Memory interface signals.
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signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
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signal s_rxfifo_rdata: std_logic_vector(8 downto 0);
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signal s_rxfifo_wen: std_logic;
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signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
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signal s_rxfifo_wdata: std_logic_vector(8 downto 0);
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signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
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signal s_txfifo_rdata: std_logic_vector(8 downto 0);
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signal s_txfifo_wen: std_logic;
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signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
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signal s_txfifo_wdata: std_logic_vector(8 downto 0);
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begin
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-- Instantiate link controller.
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link_inst: spwlink
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generic map (
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reset_time => reset_time )
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port map (
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clk => clk,
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rst => rst,
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linki => linki,
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linko => linko,
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rxen => recv_rxen,
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recvo => recvo,
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xmiti => xmiti,
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xmito => xmito );
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-- Instantiate receiver.
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recv_inst: spwrecv
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generic map(
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disconnect_time => disconnect_time,
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rxchunk => rxchunk )
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port map (
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clk => clk,
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rxen => recv_rxen,
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recvo => recvo,
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inact => recv_inact,
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inbvalid => recv_inbvalid,
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inbits => recv_inbits );
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-- Instantiate transmitter.
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xmit_sel0: if tximpl = impl_generic generate
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xmit_inst: spwxmit
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port map (
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clk => clk,
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rst => rst,
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divcnt => xmit_divcnt,
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xmiti => xmiti,
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xmito => xmito,
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spw_do => spw_do,
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spw_so => spw_so );
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end generate;
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xmit_sel1: if tximpl = impl_fast generate
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xmit_fast_inst: spwxmit_fast
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port map (
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clk => clk,
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txclk => txclk,
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rst => rst,
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divcnt => xmit_divcnt,
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xmiti => xmiti,
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xmito => xmito,
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spw_do => spw_do,
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spw_so => spw_so );
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end generate;
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-- Instantiate receiver front-end.
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recvfront_sel0: if rximpl = impl_generic generate
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recvfront_generic_inst: spwrecvfront_generic
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port map (
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clk => clk,
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rxen => recv_rxen,
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inact => recv_inact,
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inbvalid => recv_inbvalid,
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inbits => recv_inbits,
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spw_di => spw_di,
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spw_si => spw_si );
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end generate;
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recvfront_sel1: if rximpl = impl_fast generate
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recvfront_fast_inst: spwrecvfront_fast
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generic map (
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rxchunk => rxchunk )
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port map (
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clk => clk,
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rxclk => rxclk,
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rxen => recv_rxen,
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inact => recv_inact,
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inbvalid => recv_inbvalid,
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inbits => recv_inbits,
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spw_di => spw_di,
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spw_si => spw_si );
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end generate;
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|
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-- Instantiate RX memory.
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rxmem: spwram
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generic map (
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abits => rxfifosize_bits,
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dbits => 9 )
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port map (
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rclk => clk,
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wclk => clk,
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ren => '1',
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raddr => s_rxfifo_raddr,
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rdata => s_rxfifo_rdata,
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wen => s_rxfifo_wen,
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waddr => s_rxfifo_waddr,
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wdata => s_rxfifo_wdata );
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-- Instantiate TX memory.
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txmem: spwram
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|
generic map (
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abits => txfifosize_bits,
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dbits => 9 )
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port map (
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rclk => clk,
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wclk => clk,
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ren => '1',
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raddr => s_txfifo_raddr,
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rdata => s_txfifo_rdata,
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wen => s_txfifo_wen,
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waddr => s_txfifo_waddr,
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wdata => s_txfifo_wdata );
|
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|
|
|
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-- Combinatorial process
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|
process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread) is
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|
variable v: regs_type;
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|
variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0);
|
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|
variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0);
|
|
|
begin
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|
v := r;
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|
v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
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|
v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
|
|
|
|
|
|
-- Keep track of whether we are sending and/or receiving a packet.
|
|
|
if linko.rxchar = '1' then
|
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|
-- got character
|
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|
v.rxpacket := not linko.rxflag;
|
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|
end if;
|
|
|
if linko.txack = '1' then
|
|
|
-- send character
|
|
|
v.txpacket := not s_txfifo_rdata(8);
|
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|
end if;
|
|
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|
|
-- Update RX fifo pointers.
|
|
|
if (rxread = '1') and (r.rxfifo_rvalid = '1') then
|
|
|
-- read from fifo
|
|
|
v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
|
|
|
end if;
|
|
|
if r.rxfull = '0' then
|
|
|
if (linko.rxchar = '1') or (r.rxeep = '1') then
|
|
|
-- write to fifo (received char or pending EEP)
|
|
|
v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
|
|
|
end if;
|
|
|
v.rxeep := '0';
|
|
|
end if;
|
|
|
|
|
|
-- Keep track of whether the RX fifo contains valid data.
|
|
|
-- (use new value of rxfifo_raddr)
|
|
|
v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
|
|
|
|
|
|
-- Update room in RX fifo (use new value of rxfifo_waddr).
|
|
|
v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
|
|
|
v.rxfull := bool_to_logic(v_tmprxroom = 0);
|
|
|
v.rxhalff := not v_tmprxroom(v_tmprxroom'high);
|
|
|
if v_tmprxroom > 63 then
|
|
|
v.rxroom := (others => '1');
|
|
|
else
|
|
|
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
|
|
|
end if;
|
|
|
|
|
|
-- Update TX fifo pointers.
|
|
|
if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
|
|
|
-- read from fifo
|
|
|
v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
|
|
|
if s_txfifo_rdata(8) = '1' then
|
|
|
v.txdiscard := '0'; -- got EOP/EEP, stop discarding data
|
|
|
end if;
|
|
|
end if;
|
|
|
if (r.txfull = '0') and (txwrite = '1') then
|
|
|
-- write to fifo
|
|
|
v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
|
|
|
end if;
|
|
|
|
|
|
-- Keep track of whether the TX fifo contains valid data.
|
|
|
-- (use new value of txfifo_raddr)
|
|
|
v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
|
|
|
|
|
|
-- Update room in TX fifo (use new value of txfifo_waddr).
|
|
|
v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
|
|
|
v.txfull := bool_to_logic(v_tmptxroom = 0);
|
|
|
v.txhalff := not v_tmptxroom(v_tmptxroom'high);
|
|
|
|
|
|
-- If the link is lost, set a flag to discard the current packet.
|
|
|
if linko.running = '0' then
|
|
|
v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket
|
|
|
v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket
|
|
|
v.rxpacket := '0';
|
|
|
v.txpacket := '0';
|
|
|
end if;
|
|
|
|
|
|
-- Clear the discard flag when the link is explicitly disabled.
|
|
|
if linkdis = '1' then
|
|
|
v.txdiscard := '0';
|
|
|
end if;
|
|
|
|
|
|
-- Drive control signals to RX fifo.
|
|
|
s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr
|
|
|
s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep);
|
|
|
s_rxfifo_waddr <= r.rxfifo_waddr;
|
|
|
if r.rxeep = '1' then
|
|
|
s_rxfifo_wdata <= "100000001";
|
|
|
else
|
|
|
s_rxfifo_wdata <= linko.rxflag & linko.rxdata;
|
|
|
end if;
|
|
|
|
|
|
-- Drive control signals to TX fifo.
|
|
|
s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr
|
|
|
s_txfifo_wen <= (not r.txfull) and txwrite;
|
|
|
s_txfifo_waddr <= r.txfifo_waddr;
|
|
|
s_txfifo_wdata <= txflag & txdata;
|
|
|
|
|
|
-- Drive inputs to spwlink.
|
|
|
linki.autostart <= autostart;
|
|
|
linki.linkstart <= linkstart;
|
|
|
linki.linkdis <= linkdis;
|
|
|
linki.rxroom <= r.rxroom;
|
|
|
linki.tick_in <= tick_in;
|
|
|
linki.ctrl_in <= ctrl_in;
|
|
|
linki.time_in <= time_in;
|
|
|
linki.txwrite <= r.txfifo_rvalid and not r.txdiscard;
|
|
|
linki.txflag <= s_txfifo_rdata(8);
|
|
|
linki.txdata <= s_txfifo_rdata(7 downto 0);
|
|
|
|
|
|
-- Drive divcnt input to spwxmit.
|
|
|
if linko.running = '1' then
|
|
|
xmit_divcnt <= txdivcnt;
|
|
|
else
|
|
|
xmit_divcnt <= default_divcnt;
|
|
|
end if;
|
|
|
|
|
|
-- Drive outputs.
|
|
|
txrdy <= not r.txfull;
|
|
|
txhalff <= r.txhalff;
|
|
|
tick_out <= linko.tick_out;
|
|
|
ctrl_out <= linko.ctrl_out;
|
|
|
time_out <= linko.time_out;
|
|
|
rxvalid <= r.rxfifo_rvalid;
|
|
|
rxhalff <= r.rxhalff;
|
|
|
rxflag <= s_rxfifo_rdata(8);
|
|
|
rxdata <= s_rxfifo_rdata(7 downto 0);
|
|
|
started <= linko.started;
|
|
|
connecting <= linko.connecting;
|
|
|
running <= linko.running;
|
|
|
errdisc <= linko.errdisc;
|
|
|
errpar <= linko.errpar;
|
|
|
erresc <= linko.erresc;
|
|
|
errcred <= linko.errcred;
|
|
|
|
|
|
-- Reset.
|
|
|
if rst = '1' then
|
|
|
v.rxpacket := '0';
|
|
|
v.rxeep := '0';
|
|
|
v.txpacket := '0';
|
|
|
v.txdiscard := '0';
|
|
|
v.rxfifo_raddr := (others => '0');
|
|
|
v.rxfifo_waddr := (others => '0');
|
|
|
v.txfifo_raddr := (others => '0');
|
|
|
v.txfifo_waddr := (others => '0');
|
|
|
v.rxfifo_rvalid := '0';
|
|
|
v.txfifo_rvalid := '0';
|
|
|
end if;
|
|
|
|
|
|
-- Update registers.
|
|
|
rin <= v;
|
|
|
end process;
|
|
|
|
|
|
-- Update registers.
|
|
|
process (clk) is
|
|
|
begin
|
|
|
if rising_edge(clk) then
|
|
|
r <= rin;
|
|
|
end if;
|
|
|
end process;
|
|
|
|
|
|
end architecture spwstream_arch;
|
|
|
|
