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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.uart.all;
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library lpp;
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use lpp.lpp_usb.all;
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entity ftdi_async_fifo_loopback is
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generic (
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oepol : integer := 0
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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FTDI_RXF : in std_logic;
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FTDI_TXE : in std_logic;
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FTDI_SIWUA : out std_logic;
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FTDI_WR : out std_logic;
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FTDI_RD : out std_logic;
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FTDI_D_in : in std_logic_vector(7 downto 0);
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FTDI_D_out : out std_logic_vector(7 downto 0);
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FTDI_D_drive : out std_logic
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);
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end ftdi_async_fifo_loopback;
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architecture beh of ftdi_async_fifo_loopback is
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type fifo_fsm_st is (idle,waitTXE,preWrite,Write,postWrite,preRead,Read,postRead);
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signal state : fifo_fsm_st:=idle;
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signal output_en : std_logic;
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signal dready : std_logic;
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signal fifo_flush_cntr : integer := 31;
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signal fifo_siwu_pulse : std_logic_vector(3 downto 0):= (others => '1');
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begin
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acthi: if oepol = 1 generate
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output_en <= '1';
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end generate;
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actlow: if oepol = 0 generate
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output_en <= '0';
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end generate;
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FTDI_SIWUA <= '1';--fifo_siwu_pulse(0);
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process(rstn,clk)
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begin
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if rstn = '0' then
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FTDI_RD <= '1';
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FTDI_WR <= '1';
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FTDI_D_drive <= not output_en;
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elsif clk'event and clk='1' then
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if fifo_flush_cntr = 1 then
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fifo_siwu_pulse <= (others => '0');
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else
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fifo_siwu_pulse <= '1' & fifo_siwu_pulse(3 downto 1);
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end if;
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case state is
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when idle =>
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if FTDI_RXF = '0' then
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state <= preRead;
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FTDI_RD <= '0';
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end if;
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FTDI_WR <= '1';
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when preWrite =>
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FTDI_WR <= '0';
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state <= Write;
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when Write =>
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FTDI_D_drive <= not output_en;
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state <= idle;
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fifo_flush_cntr <= 31;
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when preRead =>
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state <= Read;
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when Read =>
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FTDI_D_out <= FTDI_D_in;
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FTDI_RD <= '1';
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state <= waitTXE;
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when waitTXE =>
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if FTDI_TXE = '0' then
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state <= preWrite;
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FTDI_D_drive <= output_en;
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end if;
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when others => NULL;
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end case;
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end if;
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end process;
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end beh;
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-- type dcom_uart_in_type is record
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-- read : std_ulogic;
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-- write : std_ulogic;
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-- data : std_logic_vector(7 downto 0);
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-- end record;
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-- type dcom_uart_out_type is record
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-- dready : std_ulogic; -> data from ftdi to DCOM
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-- tsempty : std_ulogic; -> not used by decom -> set to 0
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-- thempty : std_ulogic; -> tels dcom that ready to write to ftdi
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-- lock : std_ulogic; -> set to 1
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-- enable : std_ulogic; -> unused
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-- data : std_logic_vector(7 downto 0);
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-- end record;
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