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MiniSpartan6:...
MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.
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spectral_matrix_package.vhd
65 lines | 2.6 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lpp_spectral_matrix / spectral_matrix_package.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE spectral_matrix_package IS
COMPONENT spectral_matrix_switch_f0
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
error_wen : OUT STD_LOGIC);
END COMPONENT;
COMPONENT spectral_matrix_time_managment
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
update_1 : IN STD_LOGIC;
time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
END COMPONENT;
COMPONENT MS_control
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0)
fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) &
correlation_start : OUT STD_LOGIC;
correlation_auto : OUT STD_LOGIC;
correlation_done : IN STD_LOGIC);
END COMPONENT;
COMPONENT MS_calculation
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
fifo_out_wen : OUT STD_LOGIC;
fifo_out_full : IN STD_LOGIC;
correlation_start : IN STD_LOGIC;
correlation_auto : IN STD_LOGIC;
correlation_begin : OUT STD_LOGIC;
correlation_done : OUT STD_LOGIC);
END COMPONENT;
END spectral_matrix_package;