HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/leon3-APB_LCD-digilent-xc3s1600e/Makefile

MiniSpartan6:...

MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.

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      include .config

      #GRLIB=../..

      TOP=leon3mp

      BOARD=digilent-xc3s1600e

      include $(GRLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      #UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf

      #UCF=$(GRLIB)/boards/$(BOARD)/leon3mp.ucf

      UCF=leon3mp.ucf

      ISEMAPOPT="-timing"

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT="-uc leon3mp.xcf"

      SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"

      VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd

      VHDLSIMFILES=testbench.vhd

      SIMTOP=testbench

      #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

      SDCFILE=default.sdc

      BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = unisim

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip ihp gleichmann opencores usbhc spw

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \

      	usb grusbhc spacewire ata synplicity haps coremp7 hcan leon4 leon4b64 \

      	l2cache slink ascs pwm hynix gr1553b iommu

      FILESKIP = grcan.vhd i2cmst.vhd

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      #XLDFLAGS=-L./ lib3tests.a -Ttext=0x60000000

      ##################  project specific targets ##########################

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				include .config
				#GRLIB=../..
				TOP=leon3mp
				BOARD=digilent-xc3s1600e
				include $(GRLIB)/boards/$(BOARD)/Makefile.inc
				DEVICE=$(PART)-$(PACKAGE)$(SPEED)
				#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
				#UCF=$(GRLIB)/boards/$(BOARD)/leon3mp.ucf
				UCF=leon3mp.ucf
				ISEMAPOPT="-timing"
				QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
				EFFORT=high
				XSTOPT="-uc leon3mp.xcf"
				SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
				VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
				VHDLSIMFILES=testbench.vhd
				SIMTOP=testbench
				#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
				SDCFILE=default.sdc
				BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
				CLEAN=soft-clean

				TECHLIBS = unisim

				LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
				tmtc openchip ihp gleichmann opencores usbhc spw
				DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
				usb grusbhc spacewire ata synplicity haps coremp7 hcan leon4 leon4b64 \
				l2cache slink ascs pwm hynix gr1553b iommu
				FILESKIP = grcan.vhd i2cmst.vhd

				include $(GRLIB)/bin/Makefile
				include $(GRLIB)/software/leon3/Makefile
				#XLDFLAGS=-L./ lib3tests.a -Ttext=0x60000000


				################## project specific targets ##########################