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# Clocks
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NET "CLK50" PERIOD = 20 ns |LOC = "K3";
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#NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
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# LEDs
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NET "LEDS<0>" LOC="P11" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<1>" LOC="N9" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<2>" LOC="M9" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<3>" LOC="P9" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<4>" LOC="T8" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<5>" LOC="N8" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<6>" LOC="P8" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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NET "LEDS<7>" LOC="P7" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
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# DIP Switches
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NET "SW<1>" LOC="L1" |IOSTANDARD=LVTTL |PULLUP;
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NET "SW<2>" LOC="L3" |IOSTANDARD=LVTTL |PULLUP;
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NET "SW<3>" LOC="L4" |IOSTANDARD=LVTTL |PULLUP;
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NET "SW<4>" LOC="L5" |IOSTANDARD=LVTTL |PULLUP;
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NET "uart_rxd" LOC="M7" |IOSTANDARD=LVTTL;
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NET "uart_txd" LOC="N6" |IOSTANDARD=LVTTL;
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# SDRAM
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NET "dram_udqm" LOC="F15" |IOSTANDARD=LVTTL;
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NET "dram_clk" LOC="G16" |IOSTANDARD=LVTTL;
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NET "dram_cke" LOC="H16" |IOSTANDARD=LVTTL;
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NET "dram_ba_1" LOC="T14" |IOSTANDARD=LVTTL;
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NET "dram_ba_0" LOC="R14" |IOSTANDARD=LVTTL;
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NET "dram_cs_n" LOC="R1" |IOSTANDARD=LVTTL;
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NET "dram_ras_n" LOC="R2" |IOSTANDARD=LVTTL;
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NET "dram_cas_n" LOC="T4" |IOSTANDARD=LVTTL;
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NET "dram_we_n" LOC="R5" |IOSTANDARD=LVTTL;
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NET "dram_ldqm" LOC="T5" |IOSTANDARD=LVTTL;
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NET "dram_addr<0>" LOC="T15" |IOSTANDARD=LVTTL;
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NET "dram_addr<1>" LOC="R16" |IOSTANDARD=LVTTL;
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NET "dram_addr<2>" LOC="P15" |IOSTANDARD=LVTTL;
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NET "dram_addr<3>" LOC="P16" |IOSTANDARD=LVTTL;
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NET "dram_addr<4>" LOC="N16" |IOSTANDARD=LVTTL;
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NET "dram_addr<5>" LOC="M15" |IOSTANDARD=LVTTL;
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NET "dram_addr<6>" LOC="M16" |IOSTANDARD=LVTTL;
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NET "dram_addr<7>" LOC="L16" |IOSTANDARD=LVTTL;
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NET "dram_addr<8>" LOC="K15" |IOSTANDARD=LVTTL;
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NET "dram_addr<9>" LOC="K16" |IOSTANDARD=LVTTL;
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NET "dram_addr<10>" LOC="R15" |IOSTANDARD=LVTTL;
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NET "dram_addr<11>" LOC="J16" |IOSTANDARD=LVTTL;
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NET "dram_addr<12>" LOC="H15" |IOSTANDARD=LVTTL;
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NET "dram_dq<0>" LOC="T13" |IOSTANDARD=LVTTL;
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NET "dram_dq<1>" LOC="T12" |IOSTANDARD=LVTTL;
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NET "dram_dq<2>" LOC="R12" |IOSTANDARD=LVTTL;
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NET "dram_dq<3>" LOC="T9" |IOSTANDARD=LVTTL;
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NET "dram_dq<4>" LOC="R9" |IOSTANDARD=LVTTL;
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NET "dram_dq<5>" LOC="T7" |IOSTANDARD=LVTTL;
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NET "dram_dq<6>" LOC="R7" |IOSTANDARD=LVTTL;
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NET "dram_dq<7>" LOC="T6" |IOSTANDARD=LVTTL;
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NET "dram_dq<8>" LOC="F16" |IOSTANDARD=LVTTL;
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NET "dram_dq<9>" LOC="E15" |IOSTANDARD=LVTTL;
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NET "dram_dq<10>" LOC="E16" |IOSTANDARD=LVTTL;
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NET "dram_dq<11>" LOC="D16" |IOSTANDARD=LVTTL;
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NET "dram_dq<12>" LOC="B16" |IOSTANDARD=LVTTL;
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NET "dram_dq<13>" LOC="B15" |IOSTANDARD=LVTTL;
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NET "dram_dq<14>" LOC="C16" |IOSTANDARD=LVTTL;
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NET "dram_dq<15>" LOC="C15" |IOSTANDARD=LVTTL;
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#Created by Constraints Editor (xc6slx25-ftg256-3) - 2016/12/08
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INST "dram_addr(0)" TNM = dram_addr;
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INST "dram_addr(1)" TNM = dram_addr;
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INST "dram_addr(2)" TNM = dram_addr;
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INST "dram_addr(3)" TNM = dram_addr;
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INST "dram_addr(4)" TNM = dram_addr;
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INST "dram_addr(5)" TNM = dram_addr;
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INST "dram_addr(6)" TNM = dram_addr;
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INST "dram_addr(7)" TNM = dram_addr;
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INST "dram_addr(8)" TNM = dram_addr;
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INST "dram_addr(9)" TNM = dram_addr;
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INST "dram_addr(10)" TNM = dram_addr;
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INST "dram_addr(11)" TNM = dram_addr;
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INST "dram_addr(12)" TNM = dram_addr;
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INST "dram_addr(0)" TNM = dram_out;
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INST "dram_addr(1)" TNM = dram_out;
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INST "dram_addr(2)" TNM = dram_out;
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INST "dram_addr(3)" TNM = dram_out;
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INST "dram_addr(4)" TNM = dram_out;
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INST "dram_addr(5)" TNM = dram_out;
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INST "dram_addr(6)" TNM = dram_out;
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INST "dram_addr(7)" TNM = dram_out;
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INST "dram_addr(8)" TNM = dram_out;
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INST "dram_addr(9)" TNM = dram_out;
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INST "dram_addr(10)" TNM = dram_out;
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INST "dram_addr(11)" TNM = dram_out;
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INST "dram_addr(12)" TNM = dram_out;
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INST "dram_ba_0" TNM = dram_out;
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INST "dram_ba_1" TNM = dram_out;
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INST "dram_cas_n" TNM = dram_out;
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INST "dram_cke" TNM = dram_out;
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#INST "dram_clk" TNM = dram_out;
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INST "dram_cs_n" TNM = dram_out;
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INST "dram_dq(0)" TNM = dram_out;
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INST "dram_dq(1)" TNM = dram_out;
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INST "dram_dq(2)" TNM = dram_out;
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INST "dram_dq(3)" TNM = dram_out;
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INST "dram_dq(4)" TNM = dram_out;
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INST "dram_dq(5)" TNM = dram_out;
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INST "dram_dq(6)" TNM = dram_out;
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INST "dram_dq(7)" TNM = dram_out;
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INST "dram_dq(8)" TNM = dram_out;
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INST "dram_dq(9)" TNM = dram_out;
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INST "dram_dq(10)" TNM = dram_out;
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INST "dram_dq(11)" TNM = dram_out;
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INST "dram_dq(12)" TNM = dram_out;
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INST "dram_dq(13)" TNM = dram_out;
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INST "dram_dq(14)" TNM = dram_out;
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INST "dram_dq(15)" TNM = dram_out;
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INST "dram_ldqm" TNM = dram_out;
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INST "dram_ras_n" TNM = dram_out;
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INST "dram_udqm" TNM = dram_out;
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INST "dram_we_n" TNM = dram_out;
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TIMEGRP "dram_out" OFFSET = OUT 12 ns AFTER "CLK50";
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INST "dram_dq(0)" TNM = dram_in;
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INST "dram_dq(1)" TNM = dram_in;
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INST "dram_dq(2)" TNM = dram_in;
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INST "dram_dq(3)" TNM = dram_in;
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INST "dram_dq(4)" TNM = dram_in;
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INST "dram_dq(5)" TNM = dram_in;
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INST "dram_dq(6)" TNM = dram_in;
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INST "dram_dq(7)" TNM = dram_in;
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INST "dram_dq(8)" TNM = dram_in;
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INST "dram_dq(9)" TNM = dram_in;
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INST "dram_dq(10)" TNM = dram_in;
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INST "dram_dq(11)" TNM = dram_in;
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INST "dram_dq(12)" TNM = dram_in;
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INST "dram_dq(13)" TNM = dram_in;
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INST "dram_dq(14)" TNM = dram_in;
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INST "dram_dq(15)" TNM = dram_in;
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TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE "CLK50" RISING;
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