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-- Top_IIR.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.FILTERcfg.all;
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use lpp.iir_filter.all;
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entity Top_IIR is
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generic(
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Sample_SZ : integer := 18;
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ChanelsCount : integer := 1;
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Coef_SZ : integer := 9;
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CoefCntPerCel: integer := 6;
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Cels_count : integer := 5);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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-- BP : in std_logic;
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-- BPinput : in std_logic_vector(3 downto 0);
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LVLinput : in std_logic_vector(15 downto 0);
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INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
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);
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end entity;
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architecture ar_Top_IIR of Top_IIR is
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signal regs_in : in_IIR_CEL_reg;
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signal regs_out : out_IIR_CEL_reg;
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signal sample_in : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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signal sample_out : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
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signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0);
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signal sample_int : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
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--signal sample_temp : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
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begin
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ChanelLoop: for i in 0 to ChanelsCount-1 generate
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SampleLoop: for j in 0 to Sample_SZ-1 generate
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sample_in(i,j) <= sample_int(i*20+j);
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end generate;
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end generate;
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--CH2loop: for k in 0 to Sample_SZ-1 generate
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-- sample_temp(k) <= BP;
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--end generate;
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sample_int <= LVLinput(15) & LVLinput(15) & LVLinput;
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INsample <= sample_in;
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OUTsample <= sample_out;
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filter : IIR_CEL_FILTER
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generic map (0,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,1)
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port map(
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reset => reset,
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clk => clk,
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sample_clk => sample_clk,
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regs_in => regs_in,
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regs_out => regs_out,
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sample_in => sample_in,
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sample_out => sample_out,
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coefs => coefs
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);
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coefs <= CoefsInitValCst;
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regs_in.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
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regs_in.config <= (others => '1');
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end architecture;
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