HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-A3PE3kL/synthesis/.recordref

ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....

ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen. Solved in place design developpment problem on Windows, look at EGSE_ICI makefile.

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				leon3mp port ADC_in_0.SDI ADC_in[0]
				leon3mp port ADC_in_1.SDI ADC_in[1]
				leon3mp port ADC_in_2.SDI ADC_in[2]
				leon3mp port ADC_in_3.SDI ADC_in[3]
				leon3mp port ADC_in_4.SDI ADC_in[4]
				leon3mp port ADC_out.CNV ADC_out[0]
				leon3mp port ADC_out.SCK ADC_out[1]

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