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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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ENTITY lpp_waveform_snapshot_controler IS
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GENERIC (
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delta_vector_size : INTEGER := 20;
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delta_vector_size_f0_2 : INTEGER := 3
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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--REGISTER CONTROL
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reg_run : IN STD_LOGIC;
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reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
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reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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---------------------------------------------------------------------------
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-- INPUT
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coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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data_f0_valid : IN STD_LOGIC;
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data_f2_valid : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- OUTPUT
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start_snapshot_f0 : OUT STD_LOGIC;
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start_snapshot_f1 : OUT STD_LOGIC;
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start_snapshot_f2 : OUT STD_LOGIC;
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wfp_on : OUT STD_LOGIC
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);
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END lpp_waveform_snapshot_controler;
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ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
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-----------------------------------------------------------------------------
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-- WAVEFORM ON/OFF FSM
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SIGNAL state_on : STD_LOGIC;
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SIGNAL wfp_on_s : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- StartSnapshot Generator for f2, f1 and f0_pre
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SIGNAL start_snapshot_f0_pre : STD_LOGIC;
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-- SIGNAL first_decount_s : STD_LOGIC;
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SIGNAL first_decount : STD_LOGIC;
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SIGNAL first_init : STD_LOGIC;
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SIGNAL counter_delta_snapshot : INTEGER;
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-----------------------------------------------------------------------------
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-- StartSnapshot Generator for f0
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SIGNAL counter_delta_f0 : INTEGER;
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SIGNAL send_start_snapshot_f0 : STD_LOGIC;
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BEGIN -- beh
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wfp_on <= wfp_on_s;
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-----------------------------------------------------------------------------
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-- WAVEFORM ON/OFF FSM
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-----------------------------------------------------------------------------
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-- INPUT reg_run
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-- coarse_time
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-- reg_start_date
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-- OUTPUT wfp_on_s
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-----------------------------------------------------------------------------
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waveform_on_off_fsm : PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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state_on <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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IF state_on = '1' THEN -- Waveform Picker ON
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state_on <= reg_run;
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ELSE -- Waveform Picker OFF
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IF coarse_time = reg_start_date THEN
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state_on <= reg_run;
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END IF;
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END IF;
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END IF;
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END PROCESS waveform_on_off_fsm;
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wfp_on_s <= state_on;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- StartSnapshot Generator for f2, f1 and f0_pre
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-----------------------------------------------------------------------------
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-- INPUT wfp_on_s
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-- reg_delta_snapshot
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-- reg_delta_f0
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-- reg_delta_f1
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-- reg_delta_f2
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-- data_f2_valid
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-- OUTPUT start_snapshot_f0_pre
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-- start_snapshot_f1
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-- start_snapshot_f2
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-----------------------------------------------------------------------------
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--lpp_front_positive_detection_1 : lpp_front_positive_detection
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-- PORT MAP (
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-- clk => clk,
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-- rstn => rstn,
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-- sin => wfp_on_s,
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-- sout => first_decount_s);
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Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn)
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BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
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IF rstn = '0' THEN -- asynchronous reset (active low)
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counter_delta_snapshot <= 0;
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first_decount <= '1';
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first_init <= '1';
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start_snapshot_f0_pre <= '0';
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start_snapshot_f1 <= '0';
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start_snapshot_f2 <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF wfp_on_s = '0' THEN
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counter_delta_snapshot <= 0;
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first_decount <= '1';
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first_init <= '1';
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start_snapshot_f0_pre <= '0';
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start_snapshot_f1 <= '0';
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start_snapshot_f2 <= '0';
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ELSE
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start_snapshot_f0_pre <= '0';
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start_snapshot_f1 <= '0';
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start_snapshot_f2 <= '0';
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IF data_f2_valid = '1' THEN
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IF first_init = '1' THEN
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counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2));
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first_init <= '0';
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ELSE
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IF counter_delta_snapshot > 0 THEN
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counter_delta_snapshot <= counter_delta_snapshot - 1;
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ELSE
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counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot));
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first_decount <= '0';
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END IF;
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IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN
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IF first_decount = '0' THEN
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start_snapshot_f0_pre <= '1';
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END IF;
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END IF;
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IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN
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IF first_decount = '0' THEN
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start_snapshot_f1 <= '1';
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END IF;
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END IF;
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IF counter_delta_snapshot = 0 THEN
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start_snapshot_f2 <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS Decounter_Cyclic_DeltaSnapshot;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- StartSnapshot Generator for f0
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-----------------------------------------------------------------------------
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-- INPUT wfp_on_s
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-- start_snapshot_f0_pre
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-- reg_delta_snapshot
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-- reg_delta_f0_2
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-- data_f0_valid
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-- OUTPUT start_snapshot_f0
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-----------------------------------------------------------------------------
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Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn)
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BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
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IF rstn = '0' THEN -- asynchronous reset (active low)
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counter_delta_f0 <= 0;
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start_snapshot_f0 <= '0';
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send_start_snapshot_f0 <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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start_snapshot_f0 <= '0';
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IF wfp_on_s = '0' THEN
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counter_delta_f0 <= 0;
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send_start_snapshot_f0 <= '1';
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ELSE
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IF start_snapshot_f0_pre = '1' THEN
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send_start_snapshot_f0 <= '0';
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counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2));
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ELSIF data_f0_valid = '1' THEN
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IF counter_delta_f0 > 0 THEN
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send_start_snapshot_f0 <= '0';
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counter_delta_f0 <= counter_delta_f0 - 1;
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ELSE
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IF send_start_snapshot_f0 = '0' THEN
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send_start_snapshot_f0 <= '1';
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start_snapshot_f0 <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS Decounter_DeltaSnapshot_f0;
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-----------------------------------------------------------------------------
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END beh;
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