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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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library std;
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use std.textio.all;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_sim_pkg.ALL;
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ENTITY testbench IS
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GENERIC(
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tech : INTEGER := 0; --axcel,0
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Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
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);
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END;
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ARCHITECTURE behav OF testbench IS
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CONSTANT ChanelCount : INTEGER := 8;
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SIGNAL TSTAMP : INTEGER:=0;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk_98304Hz : STD_LOGIC := '0';
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SIGNAL clk_98304Hz_r : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,15 downto 0);
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SIGNAL sample : Samples(7 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_f0_val : STD_LOGIC;
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SIGNAL sample_f1_val : STD_LOGIC;
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SIGNAL sample_f2_val : STD_LOGIC;
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SIGNAL sample_f3_val : STD_LOGIC;
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL signal_f0_rec : sample_vector(0 to 5,15 downto 0);
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SIGNAL signal_f1_rec : sample_vector(0 to 5,15 downto 0);
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SIGNAL signal_f2_rec : sample_vector(0 to 5,15 downto 0);
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SIGNAL signal_f3_rec : sample_vector(0 to 5,15 downto 0);
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SIGNAL end_of_simu : STD_LOGIC := '0';
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CONSTANT half_samplig_period : time := INTEGER( REAL(1000**4) / REAL(2.0*4.0*24576.0)) * 1 ps;
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_98304Hz_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk_98304Hz <= NOT clk_98304Hz;
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WAIT FOR half_samplig_period;
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ELSE
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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clk_25M_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk <= NOT clk;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 20 ns;
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ELSE
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- LPP_LFR_FILTER
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-----------------------------------------------------------------------------
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lpp_lfr_filter_1: lpp_lfr_filter
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GENERIC MAP (
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tech => tech,
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Mem_use => Mem_use,
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RTL_DESIGN_LIGHT =>1
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)
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PORT MAP (
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sample => sample,
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sample_val => sample_val,
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sample_time => (others=>'0'),
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clk => clk,
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rstn => rstn,
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data_shaping_SP0 => '0',
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data_shaping_SP1 => '0',
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data_shaping_R0 => '0',
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data_shaping_R1 => '0',
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data_shaping_R2 => '0',
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sample_f0_val => sample_f0_val,
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sample_f1_val => sample_f1_val,
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sample_f2_val => sample_f2_val,
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sample_f3_val => sample_f3_val,
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sample_f0_wdata => sample_f0_wdata,
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sample_f1_wdata => sample_f1_wdata,
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sample_f2_wdata => sample_f2_wdata,
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sample_f3_wdata => sample_f3_wdata
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SAMPLE PULSE GENERATION
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val <= '0';
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clk_98304Hz_r <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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clk_98304Hz_r <= clk_98304Hz;
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IF clk_98304Hz = '1' AND clk_98304Hz_r = '0' THEN
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sample_val <= '1';
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ELSE
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sample_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- READ INPUT SIGNALS
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-----------------------------------------------------------------------------
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gen: sig_reader
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GENERIC MAP(
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FNAME => "input.txt",
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WIDTH => ChanelCount,
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RESOLUTION => 16,
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GAIN => 1.0
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)
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PORT MAP(
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clk => sample_val,
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end_of_simu => end_of_simu,
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out_signal => signal_gen
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);
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample(I)(J) <= signal_gen(I,J);
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END GENERATE;
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END GENERATE;
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output_splitter: FOR CHAN IN 0 TO 5 GENERATE
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bits_splitter: FOR BIT IN 0 TO 15 GENERATE
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signal_f0_rec(CHAN,BIT) <= sample_f0_wdata((CHAN*16) + BIT);
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signal_f1_rec(CHAN,BIT) <= sample_f1_wdata((CHAN*16) + BIT);
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signal_f2_rec(CHAN,BIT) <= sample_f2_wdata((CHAN*16) + BIT);
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signal_f3_rec(CHAN,BIT) <= sample_f3_wdata((CHAN*16) + BIT);
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END GENERATE bits_splitter;
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END GENERATE output_splitter;
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-----------------------------------------------------------------------------
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-- RECORD SIGNALS
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-----------------------------------------------------------------------------
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f0_rec : sig_recorder
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GENERIC MAP(
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FNAME => "output_f0.txt",
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WIDTH => 6,
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RESOLUTION => 16
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)
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PORT MAP(
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clk => sample_f0_val,
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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input_signal => signal_f0_rec
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);
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f1_rec : sig_recorder
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GENERIC MAP(
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FNAME => "output_f1.txt",
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WIDTH => 6,
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RESOLUTION => 16
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)
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PORT MAP(
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clk => sample_f1_val,
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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input_signal => signal_f1_rec
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);
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f2_rec : sig_recorder
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GENERIC MAP(
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FNAME => "output_f2.txt",
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WIDTH => 6,
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RESOLUTION => 16
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)
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PORT MAP(
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clk => sample_f2_val,
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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input_signal => signal_f2_rec
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);
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f3_rec : sig_recorder
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GENERIC MAP(
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FNAME => "output_f3.txt",
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WIDTH => 6,
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RESOLUTION => 16
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)
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PORT MAP(
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clk => sample_f3_val,
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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input_signal => signal_f3_rec
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);
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END;
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