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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- package: jtag
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-- File: jtag.vhd
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-- Author: Edvin Catovic - Gaisler Research
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-- Description: JTAG components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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package jtag is
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constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
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constant JTAG_NEXTREME : integer range 0 to 65535 := 16#102#;
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constant JTAG_IHP25RH1 : integer range 0 to 65535 := 16#251#;
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constant JTAG_NGMP_PROTO : integer range 0 to 65535 := 16#281#;
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constant JTAG_ORBITA1 : integer range 0 to 65535 := 16#631#;
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constant JTAG_UT699RH : integer range 0 to 65535 := 16#699#;
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constant JTAG_UT700RH : integer range 0 to 65535 := 16#700#;
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constant JTAG_GR702 : integer range 0 to 65535 := 16#702#;
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constant JTAG_GR712 : integer range 0 to 65535 := 16#712#;
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component ahbjtag
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generic (
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tech : integer range 0 to NTECH := 0;
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hindex : integer := 0;
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nsync : integer range 1 to 2 := 1;
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idcode : integer range 0 to 255 := 9;
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manf : integer range 0 to 2047 := 804;
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part : integer range 0 to 65535 := 0;
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ver : integer range 0 to 15 := 0;
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ainst : integer range 0 to 255 := 2;
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dinst : integer range 0 to 255 := 3;
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scantest : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0);
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapi_tdo : in std_ulogic;
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trst : in std_ulogic := '1';
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tdoen : out std_ulogic
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);
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end component;
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component ahbjtag_bsd
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generic (
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tech : integer range 0 to NTECH := 0;
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hindex : integer := 0;
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nsync : integer range 1 to 2 := 1;
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ainst : integer range 0 to 255 := 2;
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dinst : integer range 0 to 255 := 3);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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asel : in std_ulogic;
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dsel : in std_ulogic;
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tck : in std_ulogic;
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regi : in std_ulogic;
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shift : in std_ulogic;
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rego : out std_ulogic
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);
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end component;
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component bscanctrl
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generic (
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spinst: integer := 5; -- sample/preload
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etinst: integer := 6; -- extest
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itinst: integer := 7; --intest
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hzinst: integer := 8; -- highz
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clinst: integer := 9 -- clamp
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);
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port (
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trst : in std_ulogic;
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tapo_tck : in std_ulogic;
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tapo_tdi : in std_ulogic;
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tapo_inst : in std_logic_vector(7 downto 0);
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tapo_rst : in std_ulogic;
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tapo_capt : in std_ulogic;
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tapo_shft : in std_ulogic;
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tapo_upd : in std_ulogic;
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tapi_tdo : out std_ulogic;
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chain_tdi : out std_ulogic;
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chain_tdo : in std_ulogic;
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bsshft : out std_ulogic;
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bscapt : out std_ulogic;
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bsupdi : out std_ulogic;
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bsupdo : out std_ulogic;
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bsdrive : out std_ulogic;
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bshighz : out std_ulogic
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);
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end component;
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component bscanregs
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generic (
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tech: integer := 0;
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nsigs: integer range 1 to 30 := 8;
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dirmask: integer := 2#00000000#;
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enable: integer range 0 to 1 := 1
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);
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port (
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sigi: in std_logic_vector(nsigs-1 downto 0);
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sigo: out std_logic_vector(nsigs-1 downto 0);
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tck: in std_ulogic;
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tdi: in std_ulogic;
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tdo: out std_ulogic;
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bsshft: in std_ulogic;
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bscapt: in std_ulogic;
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bsupdi: in std_ulogic;
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bsupdo: in std_ulogic;
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bsdrive: in std_ulogic;
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bshighz: in std_ulogic
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);
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end component;
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component bscanregsbd
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generic (
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tech: integer:= 0;
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nsigs: integer := 8;
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enable: integer range 0 to 1 := 1;
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hzsup: integer range 0 to 1 := 1
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);
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port (
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pado : out std_logic_vector(nsigs-1 downto 0);
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padoen : out std_logic_vector(nsigs-1 downto 0);
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padi : in std_logic_vector(nsigs-1 downto 0);
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coreo : in std_logic_vector(nsigs-1 downto 0);
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coreoen : in std_logic_vector(nsigs-1 downto 0);
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corei : out std_logic_vector(nsigs-1 downto 0);
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tck : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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bsshft : in std_ulogic;
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bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
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bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
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bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
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bsdrive : in std_ulogic; -- drive outdata regs to pad,
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-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
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bshighz : in std_ulogic -- tri-state output if hzsup, sample 1 on input
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);
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end component;
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end;
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