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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.uart.all;
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library lpp;
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use lpp.lpp_usb.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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entity ahb_ftdi_fifo is
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generic (
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oepol : integer := 0;
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hindex : integer := 0
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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FTDI_RXF : in std_logic;
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FTDI_TXE : in std_logic;
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FTDI_SIWUA : out std_logic;
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FTDI_WR : out std_logic;
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FTDI_RD : out std_logic;
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FTDI_D_in : in std_logic_vector(7 downto 0);
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FTDI_D_out : out std_logic_vector(7 downto 0);
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FTDI_D_drive : out std_logic
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);
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end ahb_ftdi_fifo;
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architecture beh of ahb_ftdi_fifo is
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constant REVISION : integer := 0;
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signal dmai : ahb_dma_in_type;
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signal dmao : ahb_dma_out_type;
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signal duarti : dcom_uart_in_type;
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signal duarto : dcom_uart_out_type;
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begin
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ahbmst0 : ahbmst
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generic map (hindex => hindex, venid => VENDOR_LPP, devid => LPP_AHB_FTDI_FIFO)
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port map (rstn, clk, dmai, dmao, ahbi, ahbo);
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dcom_fifo0 : ftdi_async_fifo generic map (oepol)
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port map (clk, rstn, duarti, duarto, FTDI_RXF, FTDI_TXE, FTDI_SIWUA,
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FTDI_WR, FTDI_RD, FTDI_D_in, FTDI_D_out, FTDI_D_drive);
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dcom0 : dcom port map (rstn, clk, dmai, dmao, duarti, duarto, ahbi);
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end beh;
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