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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.general_purpose.SYNC_FF;
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-------------------------------------------------------------------------------
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ENTITY ADS7886_drvr_tb IS
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END ADS7886_drvr_tb;
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-------------------------------------------------------------------------------
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ARCHITECTURE tb OF ADS7886_drvr_tb IS
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COMPONENT TestModule_ADS7886
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GENERIC (
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freq : INTEGER;
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amplitude : INTEGER);
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PORT (
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cnv_run : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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sck : IN STD_LOGIC;
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sdo : OUT STD_LOGIC);
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END COMPONENT;
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-- component generics
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT ncycle_cnv_high : INTEGER := 79;
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CONSTANT ncycle_cnv : INTEGER := 500;
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-- component ports
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SIGNAL cnv_rstn : STD_LOGIC;
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SIGNAL cnv : STD_LOGIC;
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SIGNAL rstn : STD_LOGIC;
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SIGNAL sck : STD_LOGIC;
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SIGNAL sdo : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL run_cnv : STD_LOGIC;
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-- clock
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signal Clk : STD_LOGIC := '1';
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SIGNAL cnv_clk : STD_LOGIC := '1';
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BEGIN -- tb
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MODULE_ADS7886: FOR I IN 0 TO ChanelCount-1 GENERATE
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TestModule_ADS7886_u: TestModule_ADS7886
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GENERIC MAP (
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freq => 256/(I+1),
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amplitude => 300/(I+1))
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(I));
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END GENERATE MODULE_ADS7886;
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-- component instantiation
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DUT: ADS7886_drvr
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GENERIC MAP (
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ChanelCount => ChanelCount,
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ncycle_cnv_high => ncycle_cnv_high,
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ncycle_cnv => ncycle_cnv)
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PORT MAP (
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cnv_clk => cnv_clk,
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cnv_rstn => cnv_rstn,
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cnv_run => run_cnv,
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cnv => cnv,
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clk => clk,
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rstn => rstn,
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sck => sck,
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sdo => sdo,
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sample => sample,
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sample_val => sample_val);
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-- clock generation
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Clk <= not Clk after 20 ns; -- 25 Mhz
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cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait until Clk = '1';
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rstn <= '0';
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cnv_rstn <= '0';
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run_cnv <= '0';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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rstn <= '1';
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cnv_rstn <= '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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run_cnv <= '1';
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wait;
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end process WaveGen_Proc;
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END tb;
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-------------------------------------------------------------------------------
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CONFIGURATION ADS7886_drvr_tb_tb_cfg OF ADS7886_drvr_tb IS
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FOR tb
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END FOR;
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END ADS7886_drvr_tb_tb_cfg;
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-------------------------------------------------------------------------------
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