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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fsmdma IS
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PORT (
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-- AMBA AHB system signals
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clk : IN STD_ULOGIC;
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rstn : IN STD_ULOGIC;
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- FIFO - IN
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fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_empty_threshold : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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---------------------------------------------------------------------------
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-- DMA - OUT
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dma_fifo_valid_burst : OUT STD_LOGIC;
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dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_fifo_ren : IN STD_LOGIC;
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dma_buffer_new : OUT STD_LOGIC;
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dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
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dma_buffer_full : IN STD_LOGIC;
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dma_buffer_full_err : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- Reg In
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status_buffer_ready : IN STD_LOGIC;
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addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
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-- Reg Out
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ready_buffer : OUT STD_LOGIC;
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buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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error_buffer_full : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF lpp_waveform_fsmdma IS
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TYPE FSM_DMA_STATE IS (IDLE, ONGOING);
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SIGNAL state : FSM_DMA_STATE;
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SIGNAL burst_valid_s : STD_LOGIC;
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BEGIN
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burst_valid_s <= NOT fifo_empty_threshold;
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error_buffer_full <= dma_buffer_full_err;
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fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1';
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dma_fifo_data <= fifo_data;
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dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '0';
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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state <= IDLE;
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buffer_time <= (OTHERS => '0');
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dma_buffer_addr <= (OTHERS => '0');
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dma_buffer_length <= (OTHERS => '0');
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dma_buffer_new <= '0';
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ready_buffer <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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ready_buffer <= '0';
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dma_buffer_new <= '0';
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IF run = '1' THEN
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CASE state IS
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WHEN IDLE =>
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IF fifo_empty = '0' THEN
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IF status_buffer_ready = '0' THEN
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state <= ONGOING;
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buffer_time <= fifo_buffer_time;
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dma_buffer_addr <= addr_buffer;
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dma_buffer_length <= length_buffer;
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dma_buffer_new <= '1';
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END IF;
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END IF;
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WHEN ONGOING =>
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IF dma_buffer_full = '1' THEN
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ready_buffer <= '1';
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state <= IDLE;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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ELSE
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state <= IDLE;
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buffer_time <= (OTHERS => '0');
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dma_buffer_addr <= (OTHERS => '0');
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dma_buffer_length <= (OTHERS => '0');
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dma_buffer_new <= '0';
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END IF;
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END IF;
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END PROCESS;
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END Behavioral;
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