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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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PACKAGE lpp_leon3_soc_pkg IS
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type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
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type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
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type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
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COMPONENT leon3_soc
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GENERIC (
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fabtech : INTEGER;
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memtech : INTEGER;
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padtech : INTEGER;
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clktech : INTEGER;
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disas : INTEGER;
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dbguart : INTEGER;
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pclow : INTEGER;
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clk_freq : INTEGER;
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NB_CPU : INTEGER;
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ENABLE_FPU : INTEGER;
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FPU_NETLIST : INTEGER;
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ENABLE_DSU : INTEGER;
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ENABLE_AHB_UART : INTEGER;
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ENABLE_APB_UART : INTEGER;
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ENABLE_IRQMP : INTEGER;
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ENABLE_GPT : INTEGER;
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NB_AHB_MASTER : INTEGER;
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NB_AHB_SLAVE : INTEGER;
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NB_APB_SLAVE : INTEGER);
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PORT (
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clk : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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errorn : OUT STD_ULOGIC;
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ahbrxd : IN STD_ULOGIC;
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ahbtxd : OUT STD_ULOGIC;
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urxd1 : IN STD_ULOGIC;
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utxd1 : OUT STD_ULOGIC;
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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apbi_ext : OUT apb_slv_in_type;
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apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
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ahbi_s_ext : OUT ahb_slv_in_type;
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ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
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ahbi_m_ext : OUT AHB_Mst_In_Type;
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ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
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END COMPONENT;
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END;
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