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-- RWbuf.vhd
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library IEEE;
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use IEEE.numeric_bit.all;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity RWbuf is
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generic(DataMax : integer := 1024);
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port(
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clk : in std_logic;
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rst : in std_logic;
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flagC : in std_logic;
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flagB : in std_logic;
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IOselect : in std_logic;
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ifclk : out std_logic;
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sloe : out std_logic;
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slrd : out std_logic;
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slwr : out std_logic;
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pktend : out std_logic;
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fifoadr : out std_logic_vector(1 downto 0);
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fdbusrw : inout std_logic_vector(7 downto 0)
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);
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end entity;
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architecture ar_RWbuf of RWbuf is
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type data is array (natural range <>) of std_logic_vector(7 downto 0);
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signal send_data : data (DataMax downto 0);
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type etat is (S0,S1,S2,S3,S4,S5,S6);
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signal state : etat;
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signal Yout : std_logic_vector(7 downto 0);
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signal Sint : std_logic_vector(7 downto 0);
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signal index_data : integer range 0 to DataMax := 0;
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signal index_data_read : integer range 0 to DataMax := 0;
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component BIBUF is
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port( PAD : inout std_logic;
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D : in std_logic := 'U';
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E : in std_logic := 'U';
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Y : out std_logic);
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end component;
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begin
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io_buf0: BIBUF port map(PAD => fdbusrw(0), D=>Sint(0), E=>IOselect, Y=>Yout(0));
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io_buf1: BIBUF port map(PAD => fdbusrw(1), D=>Sint(1), E=>IOselect, Y=>Yout(1));
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io_buf2: BIBUF port map(PAD => fdbusrw(2), D=>Sint(2), E=>IOselect, Y=>Yout(2));
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io_buf3: BIBUF port map(PAD => fdbusrw(3), D=>Sint(3), E=>IOselect, Y=>Yout(3));
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io_buf4: BIBUF port map(PAD => fdbusrw(4), D=>Sint(4), E=>IOselect, Y=>Yout(4));
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io_buf5: BIBUF port map(PAD => fdbusrw(5), D=>Sint(5), E=>IOselect, Y=>Yout(5));
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io_buf6: BIBUF port map(PAD => fdbusrw(6), D=>Sint(6), E=>IOselect, Y=>Yout(6));
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io_buf7: BIBUF port map(PAD => fdbusrw(7), D=>Sint(7), E=>IOselect, Y=>Yout(7));
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ifclk <= clk;
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-- process(flagc,flagb)
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-- begin
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-- if(flagc='0' and flagb='1') then
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-- IOselect<='1';
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-- end if;
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-- if (flagc='1'and flagb='0') then
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-- IOselect<='0';
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-- end if;
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-- if(flagc='0'and flagb='0') then
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-- IOselect<='1';
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-- end if;
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-- if (flagc='1'and flagb='1') then
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-- IOselect<='0';
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-- end if;
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-- end proces
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process(clk,IOselect,rst)
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begin
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if (rst = '0') then
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state <= S0;
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slwr <= '1';
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pktend <= '1';
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sloe <= '1';
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slrd <= '1';
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elsif (clk'event and clk='1' )then
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case state is
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when S0 =>
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if (IOselect = '0') then
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state <= S1;
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fifoadr <= "00";
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index_data <= 0;
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elsif (IOselect = '1') then
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state <= S4;
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end if;
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when S1 => -- lecture de ep2
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if (flagc = '1') then --selection de EP2
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state <= S2;
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sloe<='0';
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else
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state <= S0;
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sloe <= '1';
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slrd <= '1';
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end if;
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when S2 =>
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-- V�rification: si EP2 n'est pas vide
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index_data <= index_data + 1;
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slrd <= '0';
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send_data(index_data)<=Yout; --recup�re le contenu
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state <= S3;
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when S3 =>
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state <= S1;
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slrd <= '1';
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if (index_data = 2048)then
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index_data <= 0;
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end if;
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-- ecriture dans ep6.
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when S4 => -- ECRITURE DANS EP6
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fifoadr <= "10"; --selection de EP6
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state <= S5;
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index_data_read <= 0;
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slrd <= '1';
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sloe <= '1';
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when S5 =>
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if (flagb = '1') then -- V�rification: si EP6 est plein
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index_data_read <= index_data_read +1;
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slwr <= '0';
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state <= S6;
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Sint <= send_data(index_data_read); --"01000111";
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else
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state <= S0;
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slwr <= '1';
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end if;
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when S6 =>
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slwr <= '1';
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state <= S5;
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if (index_data_read = index_data)then
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index_data_read <= 0;
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end if;
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end case;
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end if;
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end process;
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end architecture;
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