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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.lpp_cna.all;
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--! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
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entity APB_CNA is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
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SYNC : out std_logic; --! Signal de synchronisation du convertisseur
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SCLK : out std_logic; --! Horloge systeme du convertisseur
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DATA : out std_logic --! Donn�e num�rique s�rialis�
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);
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end APB_CNA;
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--! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
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--! et les sorties seront cabl�es vers le convertisseur.
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architecture ar_APB_CNA of APB_CNA is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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signal enable : std_logic;
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signal flag_sd : std_logic;
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type CNA_ctrlr_Reg is record
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CNA_Cfg : std_logic_vector(1 downto 0);
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CNA_Data : std_logic_vector(15 downto 0);
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end record;
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signal Rec : CNA_ctrlr_Reg;
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signal Rdata : std_logic_vector(31 downto 0);
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begin
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enable <= Rec.CNA_Cfg(0);
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Rec.CNA_Cfg(1) <= flag_sd;
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CONVERTER : CNA_TabloC
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port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
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process(rst,clk)
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begin
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if(rst='0')then
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Rec.CNA_Data <= (others => '0');
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elsif(clk'event and clk='1')then
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(abits-1 downto 2) is
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when "000000" =>
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Rec.CNA_Cfg(0) <= apbi.pwdata(0);
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when "000001" =>
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Rec.CNA_Data <= apbi.pwdata(15 downto 0);
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when others =>
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null;
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end case;
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end if;
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--APB READ OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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case apbi.paddr(abits-1 downto 2) is
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when "000000" =>
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Rdata(31 downto 2) <= X"ABCDEF5" & "00";
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Rdata(1 downto 0) <= Rec.CNA_Cfg;
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when "000001" =>
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Rdata(31 downto 16) <= X"FD18";
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Rdata(15 downto 0) <= Rec.CNA_Data;
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when others =>
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Rdata <= (others => '0');
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end case;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= Rdata when apbi.penable = '1';
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end ar_APB_CNA;
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