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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.Clk_divider;
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entity lpp_apb_ad_conv is
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generic(
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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ChanelCount : integer := 1;
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clkkHz : integer := 50000;
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smpClkHz : integer := 100;
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ADCref : integer := AD7688);
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Port (
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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AD_in : in AD7688_in(ChanelCount-1 downto 0);
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AD_out : out AD7688_out);
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end lpp_apb_ad_conv;
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architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADC, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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signal Rdata : std_logic_vector(31 downto 0);
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signal smpout : Samples_out(ChanelCount-1 downto 0);
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signal smplClk : STD_LOGIC;
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signal DataReady : STD_LOGIC;
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type lpp_apb_ad_conv_Reg is record
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CTRL_Reg : std_logic_vector(31 downto 0);
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sample : Samples_out(ChanelCount-1 downto 0);
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end record;
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signal r : lpp_apb_ad_conv_Reg;
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begin
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caseAD7688: if ADCref = AD7688 generate
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AD7688: AD7688_drvr
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generic map(ChanelCount,clkkHz)
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Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
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end generate;
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caseADS786: if ADCref = ADS7886 generate
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ADS7886: ADS7886_drvr
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generic map(ChanelCount,clkkHz)
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Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
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end generate;
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clkdivider: Clk_divider
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generic map(clkkHz*1000,smpClkHz)
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Port map( clk ,reset,smplClk);
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r.CTRL_Reg(0) <= DataReady;
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r.sample <= smpout;
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process(reset,clk)
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begin
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if reset = '0' then
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--r.CTRL_Reg(9 downto 0) <= (others => '0');
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elsif clk'event and clk = '1' then
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(7 downto 2) is
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when "000000" =>
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--r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
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when others =>
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end case;
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end if;
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--APB READ OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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case apbi.paddr(7 downto 2) is
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when "000000" =>
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Rdata <= r.CTRL_Reg;
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when others =>
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readC: for i in 1 to ChanelCount loop
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if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
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Rdata(15 downto 0) <= r.sample(i-1)(15 downto 0);
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end if;
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end loop;
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end case;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= Rdata when apbi.penable = '1' ;
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end ar_lpp_apb_ad_conv;
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