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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.std_logic_arith.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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ENTITY TestModule_ADS7886 IS
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GENERIC (
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freq : INTEGER := 24;
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amplitude : INTEGER := 3000;
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impulsion : INTEGER := 0 -- 1 => impulsion generation
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);
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PORT (
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-- CONV --
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cnv_run : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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-- DATA --
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sck : IN STD_LOGIC;
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sdo : OUT STD_LOGIC
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);
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END TestModule_ADS7886;
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ARCHITECTURE beh OF TestModule_ADS7886 IS
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SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL n : INTEGER := 0;
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BEGIN -- beh
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PROCESS (cnv, sck)
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BEGIN -- PROCESS
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IF cnv = '0' AND cnv'EVENT THEN
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n <= n + 1;
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IF impulsion = 1 THEN
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IF n = 1 THEN
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reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16);
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ELSE
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reg <= conv_std_logic_vector(integer(REAL(0)) , 16);
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END IF;
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ELSE
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reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
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END IF;
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ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
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reg(15) <= 'X';
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reg(14 DOWNTO 0) <= reg(15 DOWNTO 1);
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END IF;
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END PROCESS;
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sdo <= reg(0);
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END beh;
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