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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity TestbenshALU is
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end TestbenshALU;
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architecture ar_TestbenshALU of TestbenshALU is
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constant OP1sz : integer := 16;
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constant OP2sz : integer := 12;
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--IDLE =00 MAC =01 MULT =10 ADD =11
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constant IDLE : std_logic_vector(3 downto 0) := "0000";
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constant MAC : std_logic_vector(3 downto 0) := "0001";
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constant MULT : std_logic_vector(3 downto 0) := "0010";
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constant ADD : std_logic_vector(3 downto 0) := "0011";
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constant clr_mac : std_logic_vector(3 downto 0) := "0100";
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signal clk : std_logic:='0';
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signal reset : std_logic:='0';
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signal ctrl : std_logic_vector(3 downto 0):=IDLE;
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signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
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signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
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signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
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begin
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ALU1 : entity LPP_IIR_FILTER.ALU
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generic map(
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Arith_en => 1,
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Logic_en => 0,
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Input_SZ_1 => OP1sz,
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Input_SZ_2 => OP2sz
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)
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port map(
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clk => clk,
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reset => reset,
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ctrl => ctrl,
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OP1 => Operand1,
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OP2 => Operand2,
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RES => Resultat
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);
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clk <= not clk after 25 ns;
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process
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begin
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wait for 40 ns;
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reset <= '1';
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wait for 11 ns;
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Operand1 <= X"0001";
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Operand2 <= X"001";
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ctrl <= ADD;
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"100";
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"001";
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ctrl <= MULT;
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wait for 50 ns;
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Operand1 <= X"0002";
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Operand2 <= X"002";
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wait for 50 ns;
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ctrl <= clr_mac;
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"003";
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ctrl <= MAC;
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"001";
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wait for 50 ns;
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Operand1 <= X"0011";
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Operand2 <= X"003";
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wait for 50 ns;
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Operand1 <= X"1001";
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Operand2 <= X"003";
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"000";
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wait for 50 ns;
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Operand1 <= X"0001";
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Operand2 <= X"003";
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wait for 50 ns;
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Operand1 <= X"0101";
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Operand2 <= X"053";
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wait for 50 ns;
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ctrl <= clr_mac;
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wait;
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end process;
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end ar_TestbenshALU;
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