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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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ENTITY SYNC_FF IS
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GENERIC (
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NB_FF_OF_SYNC : INTEGER := 2);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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A : IN STD_LOGIC;
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A_sync : OUT STD_LOGIC);
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END SYNC_FF;
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ARCHITECTURE beh OF SYNC_FF IS
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SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0);
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BEGIN -- beh
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sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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A_temp(I) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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A_temp(I) <= A_temp(I+1);
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END IF;
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END PROCESS;
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END GENERATE sync_loop;
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A_temp(NB_FF_OF_SYNC) <= A;
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A_sync <= A_temp(0);
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END beh;
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