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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.misc.all;
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use gaisler.memctrl.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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entity ssram_plugin is
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generic (tech : integer := 0);
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port
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(
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clk : in std_logic;
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mem_ctrlr_o : in memory_out_type;
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SSRAM_CLK : out std_logic;
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nBWa : out std_logic;
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nBWb : out std_logic;
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nBWc : out std_logic;
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nBWd : out std_logic;
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nBWE : out std_logic;
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nADSC : out std_logic;
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nADSP : out std_logic;
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nADV : out std_logic;
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nGW : out std_logic;
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nCE1 : out std_logic;
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CE2 : out std_logic;
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nCE3 : out std_logic;
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nOE : out std_logic;
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MODE : out std_logic;
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ZZ : out std_logic
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);
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end entity;
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architecture ar_ssram_plugin of ssram_plugin is
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signal nADSPint : std_logic:='1';
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signal nOEint : std_logic:='1';
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signal RAMSN_reg: std_logic:='1';
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signal OEreg : std_logic:='1';
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signal nBWaint : std_logic:='1';
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signal nBWbint : std_logic:='1';
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signal nBWcint : std_logic:='1';
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signal nBWdint : std_logic:='1';
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signal nBWEint : std_logic:='1';
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signal nCE1int : std_logic:='1';
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signal CE2int : std_logic:='0';
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signal nCE3int : std_logic:='1';
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Type stateT is (idle,st1,st2,st3,st4);
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signal state : stateT;
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SIGNAL nclk : STD_LOGIC;
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begin
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process(clk , mem_ctrlr_o.RAMSN(0))
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begin
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if mem_ctrlr_o.RAMSN(0) ='1' then
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state <= idle;
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elsif clk ='1' and clk'event then
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case state is
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when idle =>
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state <= st1;
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when st1 =>
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state <= st2;
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when st2 =>
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state <= st3;
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when st3 =>
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state <= st4;
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when st4 =>
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state <= st1;
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end case;
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end if;
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end process;
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nclk <= NOT clk;
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ssram_clk_pad : outpad generic map (tech => tech)
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port map (SSRAM_CLK,nclk);
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nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
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nBWa_pad : outpad generic map (tech => tech)
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port map (nBWa,nBWaint);
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nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
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nBWb_pad : outpad generic map (tech => tech)
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port map (nBWb, nBWbint);
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nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
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nBWc_pad : outpad generic map (tech => tech)
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port map (nBWc, nBWcint);
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nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
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nBWd_pad : outpad generic map (tech => tech)
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port map (nBWd, nBWdint);
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nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
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nBWE_pad : outpad generic map (tech => tech)
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port map (nBWE, nBWEint);
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nADSC_pad : outpad generic map (tech => tech)
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port map (nADSC, '1');
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--nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
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nADSPint <= '0' when state = st1 else '1';
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process(clk)
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begin
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if clk'event and clk = '1' then
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RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
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end if;
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end process;
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nADSP_pad : outpad generic map (tech => tech)
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port map (nADSP, nADSPint);
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nADV_pad : outpad generic map (tech => tech)
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port map (nADV, '1');
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nGW_pad : outpad generic map (tech => tech)
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port map (nGW, '1');
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nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28);
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CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24));
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nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20);
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nCE1_pad : outpad generic map (tech => tech)
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port map (nCE1, nCE1int);
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CE2_pad : outpad generic map (tech => tech)
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port map (CE2, CE2int);
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nCE3_pad : outpad generic map (tech => tech)
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port map (nCE3, nCE3int);
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nOE_pad : outpad generic map (tech => tech)
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port map (nOE, nOEint);
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process(clk)
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begin
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if clk'event and clk = '1' then
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OEreg <= mem_ctrlr_o.OEN;
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end if;
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end process;
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--nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
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nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1';
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MODE_pad : outpad generic map (tech => tech)
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port map (MODE, '0');
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ZZ_pad : outpad generic map (tech => tech)
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port map (ZZ, '0');
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end architecture;
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