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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.general_purpose.all;
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--! Driver de l'ALU
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entity ALU_Driver is
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generic(
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Input_SZ_1 : integer := 16;
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Input_SZ_2 : integer := 16);
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port(
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clk : in std_logic; --! Horloge du composant
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reset : in std_logic; --! Reset general du composant
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IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
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IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
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Take : in std_logic; --! Flag, op�rande r�cup�r�
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Received : in std_logic; --! Flag, R�sultat bien ressu
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Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
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Valid : out std_logic; --! Flag, R�sultat disponible
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Read : out std_logic; --! Flag, op�rande disponible
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CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
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COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
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OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
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OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
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);
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end ALU_Driver;
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--! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
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architecture ar_ALU_Driver of ALU_Driver is
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signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
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signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
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signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
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signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
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signal go_st : std_logic;
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signal Take_reg : std_logic;
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signal Received_reg : std_logic;
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type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
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signal ect : etat;
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signal st : etat;
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begin
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process(clk,reset)
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begin
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if(reset='0')then
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ect <= eX;
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st <= e0;
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go_st <= '0';
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CTRL <= ctrl_CLRMAC;
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COMP <= "00"; -- pas de complement
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Read <= '0';
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Valid <= '0';
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Take_reg <= '0';
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Received_reg <= '0';
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elsif(clk'event and clk='1')then
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Take_reg <= Take;
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Received_reg <= Received;
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case ect is
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when eX =>
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go_st <= '0';
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Read <= '1';
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CTRL <= ctrl_CLRMAC;
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ect <= e0;
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when e0 =>
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OP1re <= IN1;
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if(Conjugate='1')then --
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OP2re <= IN1; --
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else --
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OP2re <= IN2; -- modif 23/06/11
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end if; --
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if(Take_reg='0' and Take='1')then
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read <= '0';
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ect <= e1;
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end if;
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when e1 =>
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OP1 <= OP1re;
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OP2 <= OP2re;
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CTRL <= ctrl_MAC;
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Read <= '1';
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ect <= eY;
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when eY =>
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OP1im <= IN1;
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if(Conjugate='1')then --
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OP2im <= IN1; --
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else --
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OP2im <= IN2; -- modif 23/06/11
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end if; --
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CTRL <= ctrl_IDLE;
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if(Take_reg='1' and Take='0')then
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Read <= '0';
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ect <= e2;
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end if;
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when e2 =>
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OP1 <= OP1im;
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OP2 <= OP2im;
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CTRL <= ctrl_MAC;
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ect <= eZ;
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when eZ =>
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CTRL <= ctrl_IDLE;
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go_st <= '1';
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if(Received_reg='0' and Received='1')then
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if(Conjugate='1')then
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ect <= eX;
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else
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ect <= e3;
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end if;
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end if;
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when e3 =>
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CTRL <= ctrl_CLRMAC;
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go_st <= '0';
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ect <= e4;
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when e4 =>
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OP1 <= OP1im;
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OP2 <= OP2re;
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CTRL <= ctrl_MAC;
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ect <= e5;
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when e5 =>
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OP1 <= OP1re;
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OP2 <= OP2im;
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COMP <= "10";
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ect <= eW;
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when eW =>
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CTRL <= ctrl_IDLE;
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COMP <= "00";
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go_st <= '1';
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if(Received_reg='1' and Received='0')then
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ect <= eX;
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end if;
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end case;
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---------------------------------------------------------------------------------
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case st is
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when e0 =>
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if(go_st='1')then
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st <= e1;
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end if;
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when e1 =>
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Valid <= '1';
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st <= e2;
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when e2 =>
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if(Received_reg='0' and Received='1')then
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Valid <= '0';
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if(Conjugate='1')then
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st <= eY;
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else
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st <= eX;
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end if;
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end if;
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when eX =>
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st <= e3;
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when e3 =>
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if(go_st='1')then
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st <= e4;
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end if;
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when e4 =>
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Valid <= '1';
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st <= e5;
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when e5 =>
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if(Received_reg='1' and Received='0')then
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Valid <= '0';
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st <= eY;
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end if;
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when eY =>
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st <= e0;
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when others =>
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null;
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end case;
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end if;
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end process;
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end ar_ALU_Driver;
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