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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity RAM_READER is
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Generic(
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datawidth : integer := 18;
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dacresolution : integer := 12;
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abits : integer := 8
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);
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Port (
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clk : in STD_LOGIC; --! clock input
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rstn : in STD_LOGIC; --! Active low restet input
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DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector -> connect to RAM DATA output
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ADDRESS : out STD_LOGIC_VECTOR (abits-1 downto 0); --! ADDRESS output vector -> connect to RAM read ADDRESS input
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REN : out STD_LOGIC; --! Active low read enable -> connect to RAM read enable
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DATA_OUT : out STD_LOGIC_VECTOR (dacresolution-1 downto 0); --! DATA output vector
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SMP_CLK : in STD_LOGIC; --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
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INTERLEAVED : in STD_LOGIC --! When 1, interleaved mode is actived.
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);
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end RAM_READER;
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architecture Behavioral of RAM_READER is
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CONSTANT interleaved_sz : integer := dacresolution/(datawidth-dacresolution);
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signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0');
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signal SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
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signal INTERLEAVED_SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
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signal SMP_CLK_R : STD_LOGIC;
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signal interleavedCNTR : integer range 0 to interleaved_sz;
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signal REN_R : STD_LOGIC:='1';
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signal interleave : STD_LOGIC:='0';
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signal loadEvent : STD_LOGIC:='0';
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signal loadEvent_R : STD_LOGIC:='0';
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signal loadEvent_R2 : STD_LOGIC:='0';
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begin
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REN <= REN_R;
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DATA_OUT <= SAMPLE_R;
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ADDRESS <= ADDRESS_R;
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interleave <= '1' when interleavedCNTR=interleaved_sz else '0';
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loadEvent <= SMP_CLK and not SMP_CLK_R ;
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process(clk,rstn)
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begin
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if rstn='0' then
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SMP_CLK_R <= '0';
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loadEvent_R <= '0';
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loadEvent_R2 <= '0';
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elsif clk'event and clk='1' then
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SMP_CLK_R <= SMP_CLK;
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loadEvent_R <= loadEvent;
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loadEvent_R2 <= loadEvent_R;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then
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ADDRESS_R <= (others=>'0');
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SAMPLE_R <= (others=>'0');
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INTERLEAVED_SAMPLE_R <= (others=>'0');
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REN_R <= '1';
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interleavedCNTR <= 0;
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elsif clk'event and clk='1' then
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if loadEvent = '1' then
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if(interleave='0') then
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REN_R <= '0';
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end if;
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else
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REN_R <= '1';
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end if;
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if REN_R = '0' then
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ADDRESS_R <= std_logic_vector(UNSIGNED(ADDRESS_R) + 1); --Automatic increment on each read
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end if;
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if loadEvent_R2='1' then
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if(interleave='1') then
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interleavedCNTR <= 0;
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SAMPLE_R <= INTERLEAVED_SAMPLE_R;
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else
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if interleaved='1' then
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interleavedCNTR <= interleavedCNTR + 1;
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else
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interleavedCNTR <= 0;
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end if;
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SAMPLE_R <= DATA_IN(dacresolution-1 downto 0);
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INTERLEAVED_SAMPLE_R(dacresolution-1 downto 0) <= INTERLEAVED_SAMPLE_R(datawidth-dacresolution-1 downto 0) & DATA_IN(datawidth-1 downto dacresolution);
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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