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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.general_purpose.SYNC_FF;
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ENTITY top_ad_conv_RHF1401_withFilter IS
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GENERIC(
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ChanelCount : INTEGER := 8;
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ncycle_cnv_high : INTEGER := 13;
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ncycle_cnv : INTEGER := 25;
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FILTER_ENABLED : INTEGER := 16#FF#
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);
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PORT (
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cnv_clk : IN STD_LOGIC; -- 24Mhz
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cnv_rstn : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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clk : IN STD_LOGIC; -- 25MHz
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rstn : IN STD_LOGIC;
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ADC_data : IN Samples14;
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ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END top_ad_conv_RHF1401_withFilter;
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ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
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SIGNAL cnv_cycle_counter : INTEGER;
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SIGNAL cnv_s : STD_LOGIC;
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SIGNAL cnv_sync : STD_LOGIC;
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SIGNAL cnv_sync_pre : STD_LOGIC;
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SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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SIGNAL enable_ADC : STD_LOGIC;
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SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
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SIGNAL channel_counter : INTEGER;
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CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
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SIGNAL ADC_data_selected : Samples14;
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SIGNAL ADC_data_result : Samples15;
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SIGNAL sample_counter : INTEGER;
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CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
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CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
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BEGIN
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-----------------------------------------------------------------------------
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-- CNV GEN
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-----------------------------------------------------------------------------
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PROCESS (cnv_clk, cnv_rstn)
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BEGIN -- PROCESS
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IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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cnv_cycle_counter <= 0;
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cnv_s <= '0';
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ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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IF cnv_cycle_counter < ncycle_cnv-1 THEN
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cnv_cycle_counter <= cnv_cycle_counter + 1;
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IF cnv_cycle_counter < ncycle_cnv_high THEN
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cnv_s <= '1';
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ELSE
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cnv_s <= '0';
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END IF;
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ELSE
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cnv_s <= '1';
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cnv_cycle_counter <= 0;
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END IF;
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END IF;
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END PROCESS;
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cnv <= cnv_s;
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-----------------------------------------------------------------------------
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-- SYNC CNV
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-----------------------------------------------------------------------------
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SYNC_FF_cnv : SYNC_FF
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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A => cnv_s,
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A_sync => cnv_sync);
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-----------------------------------------------------------------------------
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-- DATA GEN Output Enable
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
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cnv_sync_pre <= '0';
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enable_ADC <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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cnv_sync_pre <= cnv_sync;
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IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
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enable_ADC <= '1';
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ADC_nOE_reg(0) <= '0';
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ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
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ELSE
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enable_ADC <= NOT enable_ADC;
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IF enable_ADC = '0' THEN
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ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
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-----------------------------------------------------------------------------
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-- ADC READ DATA
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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channel_counter <= MAX_COUNTER;
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all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
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sample_reg(I) <= (OTHERS => '0');
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END LOOP all_sample_reg_init;
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sample_val <= '0';
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sample_counter <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
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channel_counter <= 0;
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ELSE
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IF channel_counter < MAX_COUNTER THEN
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channel_counter <= channel_counter + 1;
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END IF;
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END IF;
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sample_val <= '0';
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all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
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IF channel_counter = I*2 THEN
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IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
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sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
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ELSE
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sample_reg(I) <= ADC_data;
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END IF;
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END IF;
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END LOOP all_sample_reg;
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IF channel_counter = (ChanelCount-1)*2 THEN
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IF sample_counter = MAX_SAMPLE_COUNTER THEN
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sample_counter <= 0 ;
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sample_val <= '1';
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ELSE
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sample_counter <= sample_counter +1;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
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-- BEGIN -- PROCESS mux_adc
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-- CASE channel_counter IS
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-- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
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-- END CASE;
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-- END PROCESS mux_adc;
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-----------------------------------------------------------------------------
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-- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
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-----------------------------------------------------------------------------
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WITH channel_counter SELECT
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ADC_data_selected <= sample_reg(0) WHEN 0*2,
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sample_reg(1) WHEN 1*2,
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sample_reg(2) WHEN 2*2,
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sample_reg(3) WHEN 3*2,
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sample_reg(4) WHEN 4*2,
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sample_reg(5) WHEN 5*2,
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sample_reg(6) WHEN 6*2,
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sample_reg(7) WHEN 7*2,
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sample_reg(8) WHEN OTHERS ;
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-----------------------------------------------------------------------------
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-- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
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-----------------------------------------------------------------------------
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ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
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sample <= sample_reg;
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END ar_top_ad_conv_RHF1401;
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