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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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LIBRARY lpp;
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USE lpp.apb_devices_list.ALL;
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ENTITY lpp_lfr_hk IS
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GENERIC (
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pindex : INTEGER := 0;
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paddr : INTEGER := 0;
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pmask : INTEGER := 16#fff#); --! MASK field of the APB BAR);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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apbi : IN apb_slv_in_type; --! APB slave input signals
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apbo : OUT apb_slv_out_type; --! APB slave output signals
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sample_val : IN STD_LOGIC;
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sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
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);
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END lpp_lfr_hk;
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ARCHITECTURE Behavioral OF lpp_lfr_hk IS
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-----------------------------------------------------------------------------
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-- APB REG
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CONSTANT REVISION : INTEGER := 1;
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CONSTANT pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_HK_DEVICE, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask)
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);
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TYPE lpp_lfr_HK_reg IS RECORD
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temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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END RECORD;
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SIGNAL reg_hk : lpp_lfr_HK_reg;
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SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL HK_SEL_s :STD_LOGIC_VECTOR(1 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- APB REG
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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Rdata <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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--APB READ OP
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IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
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CASE apbi.paddr(7 DOWNTO 2) IS
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WHEN "000000" => Rdata(15 DOWNTO 0) <= reg_hk.temp_0;
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WHEN "000001" => Rdata(15 DOWNTO 0) <= reg_hk.temp_1;
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WHEN "000010" => Rdata(15 DOWNTO 0) <= reg_hk.temp_2;
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WHEN OTHERS => Rdata(31 DOWNTO 0) <= (others => '0');
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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apbo.pirq <= (OTHERS => '0');
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apbo.prdata <= Rdata;
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apbo.pconfig <= pconfig;
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apbo.pindex <= pindex;
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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reg_hk.temp_0 <= (OTHERS => '0');
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reg_hk.temp_1 <= (OTHERS => '0');
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reg_hk.temp_2 <= (OTHERS => '0');
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HK_SEL_s <= "00";
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_val = '1' THEN
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CASE HK_SEL_s IS
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WHEN "00" => reg_hk.temp_0 <= sample; HK_SEL_s <= "01";
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WHEN "01" => reg_hk.temp_1 <= sample; HK_SEL_s <= "10";
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WHEN "10" => reg_hk.temp_2 <= sample; HK_SEL_s <= "00";
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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HK_SEL <= HK_SEL_s;
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END Behavioral;
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