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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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-- MODIFIED by Jean-christophe PELLION
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-- jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MODIFIED by Paul LEROY
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-- paul.leroy@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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ENTITY ADS7886_drvr_v2 IS
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GENERIC(
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ChannelCount : INTEGER := 8;
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NbBitsSamples : INTEGER := 16);
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PORT (
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-- CONV --
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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-- DATA --
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
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-- SAMPLE --
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sample : OUT Samples(ChannelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END ADS7886_drvr_v2;
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ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS7886_drvr_v2 IS
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SIGNAL cnv_sync : STD_LOGIC;
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SIGNAL cnv_sync_r : STD_LOGIC;
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SIGNAL cnv_done : STD_LOGIC;
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SIGNAL sample_bit_counter : INTEGER;
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SIGNAL shift_reg : Samples_15(ChannelCount-1 DOWNTO 0);
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BEGIN
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cnv_sync <= cnv_clk;
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PROCESS (clk, rstn) -- falling edge detection on cnv_sync
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BEGIN
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IF rstn = '0' THEN
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cnv_sync_r <= '1';
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cnv_done <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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cnv_sync_r <= cnv_sync;
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cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- DATA
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN
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FOR k IN 0 TO ChannelCount-1 LOOP
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shift_reg(k)(14 downto 0) <= (OTHERS => '0');
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sample(k)(15 downto 0) <= (OTHERS => '0');
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END LOOP;
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sample_bit_counter <= 0;
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sample_val <= '0';
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SCK <= '1';
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ELSIF clk'EVENT AND clk = '1' THEN
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IF (cnv_done = '1') AND (sample_bit_counter = 0) THEN
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sample_bit_counter <= 1;
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ELSIF sample_bit_counter > 0 AND sample_bit_counter < 31 THEN
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sample_bit_counter <= sample_bit_counter + 1;
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ELSIF sample_bit_counter = 31 THEN
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sample_val <= '1';
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FOR k IN 0 TO ChannelCount-1 LOOP
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sample(k)(0) <= sdo(k);
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sample(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
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END LOOP;
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sample_bit_counter <= 0;
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ELSE
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sample_val <= '0';
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END IF;
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IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel
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FOR k IN 0 TO ChannelCount-1 LOOP
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shift_reg(k)(0) <= sdo(k);
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shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
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END LOOP;
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SCK <= '0';
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ELSE
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SCK <= '1';
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END IF;
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END IF;
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END PROCESS;
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END ar_ADS7886_drvr_v2;
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