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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:14:05 07/02/2012
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-- Design Name:
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-- Module Name: lfr_time_management - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.lpp_lfr_management.ALL;
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ENTITY lfr_time_management IS
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GENERIC (
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FIRST_DIVISION : INTEGER := 374;
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NB_SECOND_DESYNC : INTEGER := 60);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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tick : IN STD_LOGIC; -- transition signal information
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new_coarsetime : IN STD_LOGIC; -- transition signal information
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coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fine_time_new : OUT STD_LOGIC;
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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coarse_time_new : OUT STD_LOGIC
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);
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END lfr_time_management;
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ARCHITECTURE Behavioral OF lfr_time_management IS
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SIGNAL FT_max : STD_LOGIC;
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SIGNAL FT_half : STD_LOGIC;
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SIGNAL FT_wait : STD_LOGIC;
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TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
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SIGNAL state : state_fsm_time_management;
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SIGNAL fsm_desync : STD_LOGIC;
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SIGNAL fsm_transition : STD_LOGIC;
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SIGNAL set_TCU : STD_LOGIC;
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SIGNAL CT_add1 : STD_LOGIC;
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SIGNAL new_coarsetime_reg : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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new_coarsetime_reg <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF new_coarsetime = '1' THEN
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new_coarsetime_reg <= '1';
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ELSIF tick = '1' THEN
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new_coarsetime_reg <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- FINE_TIME
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-----------------------------------------------------------------------------
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fine_time_counter_1: fine_time_counter
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GENERIC MAP (
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WAITING_TIME => X"0040",
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FIRST_DIVISION => FIRST_DIVISION)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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tick => tick,
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fsm_transition => fsm_transition, -- todo
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FT_max => FT_max,
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FT_half => FT_half,
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FT_wait => FT_wait,
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fine_time => fine_time,
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fine_time_new => fine_time_new);
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-----------------------------------------------------------------------------
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-- COARSE_TIME
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-----------------------------------------------------------------------------
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coarse_time_counter_1: coarse_time_counter
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GENERIC MAP(
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NB_SECOND_DESYNC => NB_SECOND_DESYNC )
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PORT MAP (
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clk => clk,
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rstn => rstn,
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tick => tick,
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set_TCU => set_TCU, -- todo
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new_TCU => new_coarsetime_reg,
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set_TCU_value => coarsetime_reg, -- todo
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CT_add1 => CT_add1, -- todo
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fsm_desync => fsm_desync, -- todo
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FT_max => FT_max,
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coarse_time => coarse_time,
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coarse_time_new => coarse_time_new);
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-----------------------------------------------------------------------------
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-- FSM
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-----------------------------------------------------------------------------
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fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
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fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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state <= DESYNC;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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--CT_add1 <= '0';
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set_TCU <= '0';
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CASE state IS
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WHEN DESYNC =>
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IF tick = '1' THEN
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state <= SYNC;
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set_TCU <= new_coarsetime_reg;
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--IF new_coarsetime = '0' AND FT_half = '1' THEN
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-- CT_add1 <= '1';
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--END IF;
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--ELSIF FT_max = '1' THEN
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-- CT_add1 <= '1';
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END IF;
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WHEN TRANSITION =>
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IF tick = '1' THEN
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state <= SYNC;
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set_TCU <= new_coarsetime_reg;
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--IF new_coarsetime = '0' THEN
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-- CT_add1 <= '1';
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--END IF;
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ELSIF FT_wait = '1' THEN
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--CT_add1 <= '1';
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state <= DESYNC;
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END IF;
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WHEN SYNC =>
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IF tick = '1' THEN
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set_TCU <= new_coarsetime_reg;
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--IF new_coarsetime = '0' THEN
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-- CT_add1 <= '1';
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--END IF;
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ELSIF FT_max = '1' THEN
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state <= TRANSITION;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
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'1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
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'1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
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'1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
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'1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
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'0';
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END Behavioral;
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