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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:17:05 07/02/2012
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-- Design Name:
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-- Module Name: apb_lfr_time_management - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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LIBRARY lpp;
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USE lpp.apb_devices_list.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_management.ALL;
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USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
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USE lpp.lpp_cna.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY apb_lfr_management IS
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GENERIC(
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tech : INTEGER := 0;
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pindex : INTEGER := 0; --! APB slave index
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paddr : INTEGER := 0; --! ADDR field of the APB BAR
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pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
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FIRST_DIVISION : INTEGER := 374;
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NB_SECOND_DESYNC : INTEGER := 60
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);
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PORT (
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clk25MHz : IN STD_LOGIC; --! Clock
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clk24_576MHz : IN STD_LOGIC; --! secondary clock
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resetn : IN STD_LOGIC; --! Reset
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grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
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apbi : IN apb_slv_in_type; --! APB slave input signals
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apbo : OUT apb_slv_out_type; --! APB slave output signals
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---------------------------------------------------------------------------
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HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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HK_val : IN STD_LOGIC;
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HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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---------------------------------------------------------------------------
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DAC_SDO : OUT STD_LOGIC;
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DAC_SCK : OUT STD_LOGIC;
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DAC_SYNC : OUT STD_LOGIC;
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DAC_CAL_EN : OUT STD_LOGIC;
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---------------------------------------------------------------------------
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
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fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
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---------------------------------------------------------------------------
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LFR_soft_rstn : OUT STD_LOGIC
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);
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END apb_lfr_management;
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ARCHITECTURE Behavioral OF apb_lfr_management IS
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CONSTANT REVISION : INTEGER := 1;
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CONSTANT pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask)
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);
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TYPE apb_lfr_time_management_Reg IS RECORD
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ctrl : STD_LOGIC;
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soft_reset : STD_LOGIC;
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coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
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coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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LFR_soft_reset : STD_LOGIC;
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HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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END RECORD;
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SIGNAL r : apb_lfr_time_management_Reg;
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SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL force_tick : STD_LOGIC;
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SIGNAL previous_force_tick : STD_LOGIC;
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SIGNAL soft_tick : STD_LOGIC;
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SIGNAL coarsetime_reg_updated : STD_LOGIC;
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SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
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--SIGNAL coarse_time_new : STD_LOGIC;
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SIGNAL coarse_time_new_49 : STD_LOGIC;
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SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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--SIGNAL fine_time_new : STD_LOGIC;
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--SIGNAL fine_time_new_temp : STD_LOGIC;
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SIGNAL fine_time_new_49 : STD_LOGIC;
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SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL tick : STD_LOGIC;
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SIGNAL new_timecode : STD_LOGIC;
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SIGNAL new_coarsetime : STD_LOGIC;
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SIGNAL time_new_49 : STD_LOGIC;
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SIGNAL time_new : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL force_reset : STD_LOGIC;
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SIGNAL previous_force_reset : STD_LOGIC;
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SIGNAL soft_reset : STD_LOGIC;
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SIGNAL soft_reset_sync : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL previous_fine_time_bit : STD_LOGIC;
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SIGNAL rstn_LFR_TM : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- DAC
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-----------------------------------------------------------------------------
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CONSTANT PRESZ : INTEGER := 8;
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CONSTANT CPTSZ : INTEGER := 16;
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CONSTANT datawidth : INTEGER := 18;
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CONSTANT dacresolution : INTEGER := 12;
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CONSTANT abits : INTEGER := 8;
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SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
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SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
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SIGNAL Reload : STD_LOGIC;
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SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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SIGNAL WEN : STD_LOGIC;
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SIGNAL LOAD_ADDRESSN : STD_LOGIC;
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SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL INTERLEAVED : STD_LOGIC;
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SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL DAC_CAL_EN_s : STD_LOGIC;
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BEGIN
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LFR_soft_rstn <= NOT r.LFR_soft_reset;
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PROCESS(resetn, clk25MHz)
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VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
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BEGIN
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IF resetn = '0' THEN
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Rdata <= (OTHERS => '0');
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r.coarse_time_load <= (OTHERS => '0');
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r.soft_reset <= '0';
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r.ctrl <= '0';
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r.LFR_soft_reset <= '1';
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force_tick <= '0';
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previous_force_tick <= '0';
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soft_tick <= '0';
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coarsetime_reg_updated <= '0';
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--DAC
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pre <= (OTHERS => '1');
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N <= (OTHERS => '1');
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Reload <= '1';
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DATA_IN <= (OTHERS => '0');
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WEN <= '1';
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LOAD_ADDRESSN <= '1';
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ADDRESS_IN <= (OTHERS => '1');
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INTERLEAVED <= '0';
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DAC_CFG <= (OTHERS => '0');
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--
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DAC_CAL_EN_s <= '0';
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ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
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coarsetime_reg_updated <= '0';
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force_tick <= r.ctrl;
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previous_force_tick <= force_tick;
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IF (previous_force_tick = '0') AND (force_tick = '1') THEN
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soft_tick <= '1';
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ELSE
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soft_tick <= '0';
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END IF;
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force_reset <= r.soft_reset;
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previous_force_reset <= force_reset;
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IF (previous_force_reset = '0') AND (force_reset = '1') THEN
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soft_reset <= '1';
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ELSE
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soft_reset <= '0';
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END IF;
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paddr := "000000";
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paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
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Rdata <= (OTHERS => '0');
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LOAD_ADDRESSN <= '1';
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WEN <= '1';
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IF apbi.psel(pindex) = '1' THEN
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--APB READ OP
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CASE paddr(7 DOWNTO 2) IS
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WHEN ADDR_LFR_MANAGMENT_CONTROL =>
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Rdata(0) <= r.ctrl;
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Rdata(1) <= r.soft_reset;
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Rdata(2) <= r.LFR_soft_reset;
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Rdata(31 DOWNTO 3) <= (OTHERS => '0');
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WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
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Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
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WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
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Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
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WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
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Rdata(31 DOWNTO 16) <= (OTHERS => '0');
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Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
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WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
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Rdata(31 DOWNTO 16) <= (OTHERS => '0');
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Rdata(15 DOWNTO 0) <= r.HK_temp_0;
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WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
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Rdata(31 DOWNTO 16) <= (OTHERS => '0');
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Rdata(15 DOWNTO 0) <= r.HK_temp_1;
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WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
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Rdata(31 DOWNTO 16) <= (OTHERS => '0');
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Rdata(15 DOWNTO 0) <= r.HK_temp_2;
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WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
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Rdata(3 DOWNTO 0) <= DAC_CFG;
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Rdata(4) <= Reload;
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Rdata(5) <= INTERLEAVED;
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Rdata(6) <= DAC_CAL_EN_s;
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Rdata(31 DOWNTO 7) <= (OTHERS => '0');
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WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
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Rdata(PRESZ-1 DOWNTO 0) <= pre;
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Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
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WHEN ADDR_LFR_MANAGMENT_DAC_N =>
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Rdata(CPTSZ-1 DOWNTO 0) <= N;
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Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
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WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
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Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
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Rdata(31 DOWNTO abits) <= (OTHERS => '0');
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WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
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Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
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Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
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WHEN OTHERS =>
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Rdata(31 DOWNTO 0) <= (OTHERS => '0');
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END CASE;
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--APB Write OP
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IF (apbi.pwrite AND apbi.penable) = '1' THEN
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CASE paddr(7 DOWNTO 2) IS
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WHEN ADDR_LFR_MANAGMENT_CONTROL =>
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r.ctrl <= apbi.pwdata(0);
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r.soft_reset <= apbi.pwdata(1);
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r.LFR_soft_reset <= apbi.pwdata(2);
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WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
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r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
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coarsetime_reg_updated <= '1';
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WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
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DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
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Reload <= apbi.pwdata(4);
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INTERLEAVED <= apbi.pwdata(5);
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DAC_CAL_EN_s <= apbi.pwdata(6);
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WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
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pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
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WHEN ADDR_LFR_MANAGMENT_DAC_N =>
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N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
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WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
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ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
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LOAD_ADDRESSN <= '0';
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WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
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DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
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WEN <= '0';
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WHEN OTHERS =>
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NULL;
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END CASE;
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ELSE
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IF r.ctrl = '1' THEN
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r.ctrl <= '0';
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END IF;
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IF r.soft_reset = '1' THEN
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r.soft_reset <= '0';
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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apbo.pirq <= (OTHERS => '0');
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apbo.prdata <= Rdata;
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apbo.pconfig <= pconfig;
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apbo.pindex <= pindex;
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-----------------------------------------------------------------------------
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-- IN
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coarse_time <= r.coarse_time;
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fine_time <= r.fine_time;
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coarsetime_reg <= r.coarse_time_load;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- OUT
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r.coarse_time <= coarse_time_s;
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r.fine_time <= fine_time_s;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tick <= grspw_tick OR soft_tick;
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SYNC_VALID_BIT_1 : SYNC_VALID_BIT
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk_in => clk25MHz,
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clk_out => clk24_576MHz,
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rstn => resetn,
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sin => tick,
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sout => new_timecode);
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SYNC_VALID_BIT_2 : SYNC_VALID_BIT
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk_in => clk25MHz,
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clk_out => clk24_576MHz,
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rstn => resetn,
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sin => coarsetime_reg_updated,
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sout => new_coarsetime);
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SYNC_VALID_BIT_3 : SYNC_VALID_BIT
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk_in => clk25MHz,
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clk_out => clk24_576MHz,
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rstn => resetn,
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sin => soft_reset,
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sout => soft_reset_sync);
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-----------------------------------------------------------------------------
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--SYNC_FF_1 : SYNC_FF
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-- GENERIC MAP (
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-- NB_FF_OF_SYNC => 2)
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-- PORT MAP (
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-- clk => clk25MHz,
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-- rstn => resetn,
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-- A => fine_time_new_49,
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-- A_sync => fine_time_new_temp);
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--lpp_front_detection_1 : lpp_front_detection
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-- PORT MAP (
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-- clk => clk25MHz,
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-- rstn => resetn,
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-- sin => fine_time_new_temp,
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-- sout => fine_time_new);
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--SYNC_VALID_BIT_4 : SYNC_VALID_BIT
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-- GENERIC MAP (
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-- NB_FF_OF_SYNC => 2)
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-- PORT MAP (
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-- clk_in => clk24_576MHz,
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-- clk_out => clk25MHz,
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-- rstn => resetn,
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-- sin => coarse_time_new_49,
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-- sout => coarse_time_new);
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time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
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SYNC_VALID_BIT_4 : SYNC_VALID_BIT
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk_in => clk24_576MHz,
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clk_out => clk25MHz,
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rstn => resetn,
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sin => time_new_49,
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sout => time_new);
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PROCESS (clk25MHz, resetn)
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BEGIN -- PROCESS
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|
|
IF resetn = '0' THEN -- asynchronous reset (active low)
|
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|
fine_time_s <= (OTHERS => '0');
|
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|
coarse_time_s <= (OTHERS => '0');
|
|
|
ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
|
|
|
IF time_new = '1' THEN
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|
fine_time_s <= fine_time_49;
|
|
|
coarse_time_s <= coarse_time_49;
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|
|
END IF;
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|
|
END IF;
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|
|
END PROCESS;
|
|
|
|
|
|
|
|
|
rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
|
|
|
'0' WHEN soft_reset_sync = '1' ELSE
|
|
|
'1';
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- LFR_TIME_MANAGMENT
|
|
|
-----------------------------------------------------------------------------
|
|
|
lfr_time_management_1 : lfr_time_management
|
|
|
GENERIC MAP (
|
|
|
FIRST_DIVISION => FIRST_DIVISION,
|
|
|
NB_SECOND_DESYNC => NB_SECOND_DESYNC)
|
|
|
PORT MAP (
|
|
|
clk => clk24_576MHz,
|
|
|
rstn => rstn_LFR_TM,
|
|
|
|
|
|
tick => new_timecode,
|
|
|
new_coarsetime => new_coarsetime,
|
|
|
coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
|
|
|
|
|
|
fine_time => fine_time_49,
|
|
|
fine_time_new => fine_time_new_49,
|
|
|
coarse_time => coarse_time_49,
|
|
|
coarse_time_new => coarse_time_new_49);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- HK
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
PROCESS (clk25MHz, resetn)
|
|
|
CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
|
|
|
-- for each HK, the update frequency is freq/3
|
|
|
--
|
|
|
-- for 14, the update frequency is
|
|
|
-- 4Hz and update for each
|
|
|
-- HK is 1.33Hz
|
|
|
BEGIN -- PROCESS
|
|
|
IF resetn = '0' THEN -- asynchronous reset (active low)
|
|
|
|
|
|
r.HK_temp_0 <= (OTHERS => '0');
|
|
|
r.HK_temp_1 <= (OTHERS => '0');
|
|
|
r.HK_temp_2 <= (OTHERS => '0');
|
|
|
|
|
|
HK_sel_s <= "00";
|
|
|
|
|
|
previous_fine_time_bit <= '0';
|
|
|
|
|
|
ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
|
|
|
|
|
|
IF HK_val = '1' THEN
|
|
|
IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
|
|
|
previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
|
|
|
CASE HK_sel_s IS
|
|
|
WHEN "00" =>
|
|
|
r.HK_temp_0 <= HK_sample;
|
|
|
HK_sel_s <= "01";
|
|
|
WHEN "01" =>
|
|
|
r.HK_temp_1 <= HK_sample;
|
|
|
HK_sel_s <= "10";
|
|
|
WHEN "10" =>
|
|
|
r.HK_temp_2 <= HK_sample;
|
|
|
HK_sel_s <= "00";
|
|
|
WHEN OTHERS => NULL;
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
HK_sel <= HK_sel_s;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- DAC
|
|
|
-----------------------------------------------------------------------------
|
|
|
cal : lfr_cal_driver
|
|
|
GENERIC MAP(
|
|
|
tech => tech,
|
|
|
PRESZ => PRESZ,
|
|
|
CPTSZ => CPTSZ,
|
|
|
datawidth => datawidth,
|
|
|
abits => abits
|
|
|
)
|
|
|
PORT MAP(
|
|
|
clk => clk25MHz,
|
|
|
rstn => resetn,
|
|
|
|
|
|
pre => pre,
|
|
|
N => N,
|
|
|
Reload => Reload,
|
|
|
DATA_IN => DATA_IN,
|
|
|
WEN => WEN,
|
|
|
LOAD_ADDRESSN => LOAD_ADDRESSN,
|
|
|
ADDRESS_IN => ADDRESS_IN,
|
|
|
ADDRESS_OUT => ADDRESS_OUT,
|
|
|
INTERLEAVED => INTERLEAVED,
|
|
|
DAC_CFG => DAC_CFG,
|
|
|
|
|
|
SYNC => DAC_SYNC,
|
|
|
DOUT => DAC_SDO,
|
|
|
SCLK => DAC_SCK,
|
|
|
SMPCLK => OPEN --DAC_SMPCLK
|
|
|
);
|
|
|
|
|
|
DAC_CAL_EN <= DAC_CAL_EN_s;
|
|
|
END Behavioral;
|
|
|
|
