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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.lpp_AMR.all;
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--! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
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entity APB_AMR is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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clkH : in std_logic;
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clk_MOD : out std_logic; --! Horloge de sortie, Modulation
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clk_DMOD : out std_logic; --! Horloge de sortie, Demodulation
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end APB_AMR;
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architecture ar_APB_AMR of APB_AMR is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_BALISE, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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type AMR_ctrlr_Reg is record
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AMR_CTRL : std_logic_vector(31 downto 0);
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AMR_FREQ : std_logic_vector(31 downto 0);
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AMR_PHI : std_logic_vector(31 downto 0);
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end record;
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signal Rec : AMR_ctrlr_Reg := ((others => '0'),std_logic_vector(to_unsigned(149,32)),std_logic_vector(to_unsigned(4,32)));
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signal Rdata : std_logic_vector(31 downto 0);
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signal Div : integer range 250 to 1024*1024;
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signal Phi : integer range 4 to 1024*8;
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signal Stop_count : std_logic;
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begin
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DEF0 : entity work.Dephaseur
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port map(clk,rst,Div,Phi,Stop_count,clk_MOD,clk_DMOD);
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Div <= to_integer(unsigned(Rec.AMR_FREQ(19 downto 0)));
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Phi <= to_integer(unsigned(Rec.AMR_PHI(12 downto 0)));
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Stop_count <= Rec.AMR_CTRL(0);
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process(rst,clk)
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begin
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if(rst='0')then
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Rec.AMR_CTRL <= (others => '0');
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Rec.AMR_FREQ <= std_logic_vector(to_unsigned(149,32));
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Rec.AMR_PHI <= std_logic_vector(to_unsigned(4,32));
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elsif(clk'event and clk='1')then
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(abits-1 downto 2) is
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when "000000" =>
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Rec.AMR_CTRL <= apbi.pwdata;
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when "000001" =>
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Rec.AMR_FREQ <= apbi.pwdata;
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when "000010" =>
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Rec.AMR_PHI <= apbi.pwdata;
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when others =>
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null;
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end case;
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end if;
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--APB READ OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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case apbi.paddr(abits-1 downto 2) is
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when "000000" =>
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Rdata <= Rec.AMR_CTRL;
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when "000001" =>
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Rdata <= Rec.AMR_FREQ;
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when "000010" =>
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Rdata <= Rec.AMR_PHI;
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when others =>
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Rdata <= (others => '0');
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end case;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= Rdata when apbi.penable = '1';
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end ar_APB_AMR;
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