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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY RAM_CEL IS
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GENERIC(
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DataSz : INTEGER RANGE 1 TO 32 := 8;
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abits : INTEGER RANGE 2 TO 12 := 8);
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PORT(
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WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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WEN, REN : IN STD_LOGIC;
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WADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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RADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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RWCLK, RESET : IN STD_LOGIC
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) ;
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END RAM_CEL;
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ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
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CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0');
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CONSTANT MAX : INTEGER := 2**(abits);
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TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit);
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SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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BEGIN
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RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
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PROCESS(RWclk, reset)
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BEGIN
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IF reset = '0' THEN
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RD <= VectInit;
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rst : FOR i IN 0 TO MAX-1 LOOP
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RAMarray(i) <= (OTHERS => '0');
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END LOOP;
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ELSIF RWclk'EVENT AND RWclk = '1' THEN
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-- IF REN = '0' THEN
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RD <= RD_int;
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-- END IF;
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IF REN = '0' THEN
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RADDR_reg <= RADDR;
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END IF;
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IF WEN = '0' THEN
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RAMarray(to_integer(UNSIGNED(WADDR))) <= WD;
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END IF;
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END IF;
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END PROCESS;
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END ar_RAM_CEL;
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