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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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Sample_SZ : INTEGER := 16;
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Coef_SZ : INTEGER := 9;
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Coef_Nb : INTEGER := 30;
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Coef_sel_SZ : INTEGER := 5
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);
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PORT(
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- PARAMETER
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virg_pos : IN INTEGER;
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coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
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-- CONTROL
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in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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--
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ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_write : IN STD_LOGIC;
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ram_read : IN STD_LOGIC;
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raddr_rst : IN STD_LOGIC;
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raddr_add1 : IN STD_LOGIC;
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waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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--
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alu_sel_input : IN STD_LOGIC;
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alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
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alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
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alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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-- DATA
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sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
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);
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END IIR_CEL_CTRLR_v2_DATAFLOW;
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ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
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COMPONENT RAM_CTRLR_v2
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GENERIC (
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tech : INTEGER;
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Input_SZ_1 : INTEGER;
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Mem_use : INTEGER);
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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ram_write : IN STD_LOGIC;
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ram_read : IN STD_LOGIC;
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raddr_rst : IN STD_LOGIC;
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raddr_add1 : IN STD_LOGIC;
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waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
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END COMPONENT;
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SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
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SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
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SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
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SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- INPUT
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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reg_sample_in <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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CASE in_sel_src IS
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WHEN "00" => reg_sample_in <= reg_sample_in;
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WHEN "01" => reg_sample_in <= sample_in;
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WHEN "10" => reg_sample_in <= ram_output;
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WHEN "11" => reg_sample_in <= alu_output;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- RAM + CTRL
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-----------------------------------------------------------------------------
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ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
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alu_output WHEN ram_sel_Wdata = "01" ELSE
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ram_output;
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RAM_CTRLR_v2_1: RAM_CTRLR_v2
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GENERIC MAP (
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tech => tech,
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Input_SZ_1 => Sample_SZ,
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Mem_use => Mem_use)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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ram_write => ram_write,
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ram_read => ram_read,
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raddr_rst => raddr_rst,
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raddr_add1 => raddr_add1,
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waddr_previous => waddr_previous,
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sample_in => ram_input,
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sample_out => ram_output);
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-----------------------------------------------------------------------------
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-- MAC_ACC
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-----------------------------------------------------------------------------
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-- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
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-- Data In : mac_sample, mac_coef
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-- Data Out: mac_output
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alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
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coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
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coeff_in: IF I < Coef_Nb GENERATE
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all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
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arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
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END GENERATE all_bit;
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END GENERATE coeff_in;
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coeff_null: IF I > (Coef_Nb -1) GENERATE
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all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
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arrayCoeff(I,J) <= '0';
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END GENERATE all_bit;
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END GENERATE coeff_null;
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END GENERATE coefftable;
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Coeff_Mux : MUXN
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GENERIC MAP (
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Input_SZ => Coef_SZ,
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NbStage => Coef_sel_SZ)
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PORT MAP (
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sel => alu_sel_coeff,
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INPUT => arrayCoeff,
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RES => alu_coef_s);
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all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
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alu_coef(J) <= alu_coef_s(J);
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END GENERATE all_bit;
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-----------------------------------------------------------------------------
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-- TODO : just for Synthesis test
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--PROCESS (clk, rstn)
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--BEGIN
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-- IF rstn = '0' THEN
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-- alu_coef <= (OTHERS => '0');
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-- ELSIF clk'event AND clk = '1' THEN
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-- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
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-- alu_coef(J) <= alu_coef_s(J);
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-- END LOOP all_bit;
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-- END IF;
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--END PROCESS;
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-----------------------------------------------------------------------------
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ALU_1: ALU
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GENERIC MAP (
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Arith_en => 1,
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Input_SZ_1 => Sample_SZ,
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Input_SZ_2 => Coef_SZ,
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COMP_EN => 1)
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PORT MAP (
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clk => clk,
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reset => rstn,
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ctrl => alu_ctrl,
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comp => alu_comp,
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OP1 => alu_sample,
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OP2 => alu_coef,
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RES => alu_output_s);
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alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
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sample_out <= alu_output;
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END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
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