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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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ENTITY cic IS
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GENERIC (
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D_delay_number : INTEGER := 2;
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S_stage_number : INTEGER := 3;
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R_downsampling_decimation_factor : INTEGER := 16;
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b_data_size : INTEGER := 16;
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b_grow : INTEGER := 5 --
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC
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);
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END cic;
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ARCHITECTURE beh OF cic IS
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TYPE data_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b_data_size + b_grow - 1 DOWNTO 0);
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SIGNAL I_data : data_vector(S_stage_number DOWNTO 0);
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SIGNAL I_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
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SIGNAL C_data : data_vector(S_stage_number DOWNTO 0);
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SIGNAL C_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
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BEGIN -- beh
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-----------------------------------------------------------------------------
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I_valid(0) <= data_in_valid;
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I_data(0)(b_data_size-1 DOWNTO 0) <= data_in;
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all_bit_grow: FOR I IN 0 TO b_grow-1 GENERATE
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I_data(0)(I+b_data_size) <= data_in(b_data_size-1);
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END GENERATE all_bit_grow;
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-----------------------------------------------------------------------------
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all_I: FOR S_i IN 1 TO S_stage_number GENERATE
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I_1: cic_integrator
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GENERIC MAP (
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b_data_size => b_data_size + b_grow)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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data_in => I_data(S_i-1),
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data_in_valid => I_valid(S_i-1),
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data_out => I_data(S_i),
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data_out_valid => I_valid(S_i)
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);
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END GENERATE all_I;
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-----------------------------------------------------------------------------
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cic_downsampler_1: cic_downsampler
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GENERIC MAP (
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R_downsampling_decimation_factor => R_downsampling_decimation_factor,
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b_data_size => b_data_size + b_grow)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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data_in => I_data(S_stage_number),
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data_in_valid => I_valid(S_stage_number),
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data_out => C_data(0),
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data_out_valid => C_valid(0));
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-----------------------------------------------------------------------------
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all_C: FOR S_i IN 1 TO S_stage_number GENERATE
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cic_comb_1: cic_comb
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GENERIC MAP (
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b_data_size => b_data_size + b_grow,
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D_delay_number => D_delay_number)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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data_in => C_data(S_i-1),
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data_in_valid => C_valid(S_i-1),
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data_out => C_data(S_i),
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data_out_valid => C_valid(S_i));
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END GENERATE all_C;
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-----------------------------------------------------------------------------
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data_out <= C_data(S_stage_number)(b_data_size + b_grow - 1 DOWNTO b_grow);
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data_out_valid <= C_valid(S_stage_number);
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-----------------------------------------------------------------------------
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END beh;
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