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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Entity: svga2ch7301c
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-- File: svga2ch7301c.vhd
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-- Author: Jan Andersson - Aeroflex Gaisler AB
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-- jan@gaisler.com
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--
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-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
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-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
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-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
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-- template designs.
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--
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-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
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-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
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--
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-- IDF Description
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-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
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-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
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-- 2 8-bit multiplexed RGB input (16-bit color, 565)
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-- 3 8-bit multiplexed RGB input (15-bit color, 555)
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--
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-- This core assumes a 100 MHz input clock on the 'clk' input.
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--
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-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
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-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
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-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
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-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
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-- Note that if dynamic selection is enabled you will need to reconfigure
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-- the DVI transmitter when the VGA core changes bit depth.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.misc.all;
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library grlib;
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use grlib.stdlib.all;
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-- pragma translate_off
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library unisim;
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use unisim.BUFG;
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use unisim.DCM;
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-- pragma translate_on
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library techmap;
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use techmap.gencomp.all;
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entity svga2ch7301c is
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generic (
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tech : integer := 0;
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idf : integer := 0;
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dynamic : integer := 0
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);
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port (
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clk : in std_ulogic;
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vgao : in apbvga_out_type;
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vgaclk : in std_ulogic;
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dclk_p : out std_ulogic;
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dclk_n : out std_ulogic;
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data : out std_logic_vector(11 downto 0);
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hsync : out std_ulogic;
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vsync : out std_ulogic;
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de : out std_ulogic
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);
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end svga2ch7301c;
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architecture rtl of svga2ch7301c is
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component BUFG port (O : out std_logic; I : in std_logic); end component;
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component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
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I1 : in std_ulogic; S : in std_ulogic);
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end component;
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signal nvgaclk : std_ulogic;
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signal vcc, gnd : std_logic;
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signal d0, d1 : std_logic_vector(11 downto 0);
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signal red, green, blue : std_logic_vector(7 downto 0);
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signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
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signal clkval : std_logic_vector(1 downto 0);
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begin -- rtl
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vcc <= '1'; gnd <= '0';
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-----------------------------------------------------------------------------
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-- RGB data multiplexer
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-----------------------------------------------------------------------------
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red <= vgao.video_out_r;
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green <= vgao.video_out_g;
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blue <= vgao.video_out_b;
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static: if dynamic = 0 generate
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idf0: if (idf = 0) generate
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d0 <= green(3 downto 0) & blue(7 downto 0);
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d1 <= red(7 downto 0) & green(7 downto 4);
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end generate;
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idf1: if (idf = 1) generate
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d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
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d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
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end generate;
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idf2: if (idf = 2) generate
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d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
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d0(3 downto 0) <= (others => '0');
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d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
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d1(3 downto 0) <= (others => '0');
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data(3 downto 0) <= (others => '0');
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end generate;
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idf3: if (idf = 3) generate
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d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
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d0(3 downto 0) <= (others => '0');
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d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
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d1(3 downto 0) <= (others => '0');
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data(3 downto 0) <= (others => '0');
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end generate idf3;
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-- DDR regs
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dataregs: for i in 11 downto (4*(idf/2)) generate
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ddr_oreg0 : ddr_oreg generic map (tech)
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port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
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d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
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end generate;
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end generate;
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nvgaclk <= not vgaclk;
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nostatic: if dynamic /= 0 generate
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d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
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green(4 downto 2) & blue(7 downto 3) & "0000";
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d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
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red(7 downto 3) & green(7 downto 5) & "0000";
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dataregs: for i in 11 downto 0 generate
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ddr_oreg0 : ddr_oreg generic map (tech)
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port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
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d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
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end generate;
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end generate;
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-----------------------------------------------------------------------------
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-- Sync signals
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-----------------------------------------------------------------------------
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process (vgaclk)
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begin -- process
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if rising_edge(vgaclk) then
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hsync <= vgao.hsync;
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vsync <= vgao.vsync;
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de <= vgao.blank;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Clock generation
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-----------------------------------------------------------------------------
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ddroreg_p : ddr_oreg generic map (tech)
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port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
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d1 => vcc, d2 => gnd, r => gnd, s => gnd);
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ddroreg_n : ddr_oreg generic map (tech)
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port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
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d1 => gnd, d2 => vcc, r => gnd, s => gnd);
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end rtl;
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