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[Library]
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grlib = modelsim/grlib
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proasic3 = modelsim/proasic3
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synplify = modelsim/synplify
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techmap = modelsim/techmap
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spw = modelsim/spw
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eth = modelsim/eth
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opencores = modelsim/opencores
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gaisler = modelsim/gaisler
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esa = modelsim/esa
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fmf = modelsim/fmf
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spansion = modelsim/spansion
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gsi = modelsim/gsi
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lpp = modelsim/lpp
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cypress = modelsim/cypress
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work = modelsim/work
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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vital2000 = $MODEL_TECH/../vital2000
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verilog = $MODEL_TECH/../verilog
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arithmetic = $MODEL_TECH/../arithmetic
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mgc_portable = $MODEL_TECH/../mgc_portable
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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[vcom]
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; Turn on VHDL-1993 as the default. Normally is off.
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VHDL93 = 1
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; Show source line containing error. Default is off.
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Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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Explicit = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = false
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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; NoVital = 1
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; Turn off inclusion of debugging info within design units. Default is to include.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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[vlog]
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; Turn off inclusion of debugging info within design units. Default is to include.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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[vsim]
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; vopt flow
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; Set to turn on automatic optimization of a design.
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; Default is off (pre-6.0 flow without vopt).
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VoptFlow = 0
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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Resolution = 1ps
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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UserTimeUnit = ns
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; Default run length
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RunLength = 100
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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; Directive to license manager:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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; nomgc Do not look for Mentor Graphics Licenses
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; nomti Do not look for Model Technology Licenses
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; noqueue Do not wait in the license queue when a license isn't available
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; License = plus
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; Stop the simulator after an assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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BreakOnAssertion = 3
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; Assertion Message Format
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; %S - Severity Level
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; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
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; %I - Instance or Region pathname (if available)
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; %% - print '%' character
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; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; Default radix for all windows and commands...
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = symbolic
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; VSIM Startup command
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; Startup = do startup.do
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; File for saving command transcript
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TranscriptFile = transcript
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; Specify whether paths in simulator commands should be described
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; in VHDL or Verilog format. For VHDL, PathSeparator = /
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; for Verilog, PathSeparator = .
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PathSeparator = /
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; Disable assertion messages
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; IgnoreNote = 1
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; IgnoreWarning = 1
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; IgnoreError = 1
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; IgnoreFailure = 1
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; Default force kind. May be freeze, drive, or deposit
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; or in other terms, fixed, wired or charged.
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; DefaultForceKind = freeze
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; If zero, open files when elaborated
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; else open files on first read or write
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; DelayFileOpen = 0
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; Control VHDL files opened for write
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; 0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
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; This controls the number of characters of a signal name
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; shown in the waveform window and the postscript plot.
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; The default value or a value of zero tells VSIM to display
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; the full name.
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; WaveSignalNameWidth = 10
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; Turn off warnings from the std_logic_arith, std_logic_unsigned
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; and std_logic_signed packages.
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StdArithNoWarnings = 1
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; Turn off warnings from the IEEE numeric_std and numeric_bit
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; packages.
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NumericStdNoWarnings = 1
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; Control the format of a generate statement label. Don't quote it.
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; GenerateFormat = %s__%d
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; Specify whether checkpoint files should be compressed.
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; The default is to be compressed.
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
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; Veriuser = veriuser.sl
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[lmc]
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
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libsm = $MODEL_TECH/libsm.sl
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
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; libsm = $MODEL_TECH/libsm.dll
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; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
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; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
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; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
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; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
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; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
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; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
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; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
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; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
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; and run "vsim.swift".
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; Logic Modeling's SmartModel SWIFT software (Windows NT)
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; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
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; ModelSim's interface to Logic Modeling's hardware modeler SFI software
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libhm = $MODEL_TECH/libhm.sl
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; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
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; libhm = $MODEL_TECH/libhm.dll
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; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
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; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
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; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
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; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
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; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
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; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
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; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
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; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
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; Logic Modeling's hardware modeler SFI software (Window NT)
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; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
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[Project]
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Project_Version = 5
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Project_DefaultLib = work
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Project_SortMethod = unused
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Project_Files_Count = 347
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Project_File_0 = ../../lib/grlib/stdlib/version.vhd
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Project_File_P_0 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 0 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_1 = ../../lib/grlib/stdlib/config.vhd
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Project_File_P_1 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 1 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_2 = ../../lib/grlib/stdlib/stdlib.vhd
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Project_File_P_2 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 2 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_3 = ../../lib/grlib/stdlib/stdio.vhd
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Project_File_P_3 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 3 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_4 = ../../lib/grlib/stdlib/testlib.vhd
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Project_File_P_4 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 4 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_5 = ../../lib/grlib/util/util.vhd
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Project_File_P_5 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 5 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_6 = ../../lib/grlib/sparc/sparc.vhd
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Project_File_P_6 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 6 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_7 = ../../lib/grlib/sparc/sparc_disas.vhd
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Project_File_P_7 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 7 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_8 = ../../lib/grlib/sparc/cpu_disas.vhd
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Project_File_P_8 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 8 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_9 = ../../lib/grlib/modgen/multlib.vhd
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Project_File_P_9 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 9 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_10 = ../../lib/grlib/modgen/leaves.vhd
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Project_File_P_10 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 10 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_11 = ../../lib/grlib/amba/amba.vhd
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Project_File_P_11 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 11 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_12 = ../../lib/grlib/amba/devices.vhd
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Project_File_P_12 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 12 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_13 = ../../lib/grlib/amba/defmst.vhd
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|
Project_File_P_13 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 13 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_14 = ../../lib/grlib/amba/apbctrl.vhd
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|
Project_File_P_14 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 14 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_15 = ../../lib/grlib/amba/ahbctrl.vhd
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|
Project_File_P_15 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 15 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_16 = ../../lib/grlib/amba/dma2ahb_pkg.vhd
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|
Project_File_P_16 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 16 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_17 = ../../lib/grlib/amba/dma2ahb.vhd
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Project_File_P_17 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 17 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_18 = ../../lib/grlib/amba/dma2ahb_tp.vhd
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Project_File_P_18 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 18 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_19 = ../../lib/grlib/amba/amba_tp.vhd
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Project_File_P_19 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to grlib compile_order 19 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_20 = ../../lib/tech/proasic3/components/proasic3.vhd
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Project_File_P_20 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to proasic3 compile_order 20 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_21 = ../../lib/synplify/sim/synplify.vhd
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Project_File_P_21 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to synplify compile_order 21 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_22 = ../../lib/synplify/sim/synattr.vhd
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Project_File_P_22 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to synplify compile_order 22 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_23 = ../../lib/techmap/gencomp/gencomp.vhd
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Project_File_P_23 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 23 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_24 = ../../lib/techmap/gencomp/netcomp.vhd
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Project_File_P_24 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 24 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_25 = ../../lib/techmap/inferred/memory_inferred.vhd
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Project_File_P_25 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 25 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_26 = ../../lib/techmap/inferred/ddr_inferred.vhd
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Project_File_P_26 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 26 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_27 = ../../lib/techmap/inferred/mul_inferred.vhd
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Project_File_P_27 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 27 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_28 = ../../lib/techmap/inferred/ddr_phy_inferred.vhd
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Project_File_P_28 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 28 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_29 = ../../lib/techmap/dware/mul_dware.vhd
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Project_File_P_29 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 29 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_30 = ../../lib/techmap/proasic3/memory_apa3.vhd
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|
Project_File_P_30 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 30 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_31 = ../../lib/techmap/proasic3/buffer_apa3.vhd
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|
Project_File_P_31 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 31 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_32 = ../../lib/techmap/proasic3/clkgen_proasic3.vhd
|
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|
Project_File_P_32 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 32 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_33 = ../../lib/techmap/proasic3/tap_proasic3.vhd
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|
Project_File_P_33 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 33 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_34 = ../../lib/techmap/maps/allclkgen.vhd
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|
Project_File_P_34 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 34 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_35 = ../../lib/techmap/maps/allddr.vhd
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|
Project_File_P_35 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 35 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_36 = ../../lib/techmap/maps/allmem.vhd
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|
Project_File_P_36 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 36 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_37 = ../../lib/techmap/maps/allmul.vhd
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|
Project_File_P_37 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 37 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_38 = ../../lib/techmap/maps/allpads.vhd
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|
Project_File_P_38 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 38 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_39 = ../../lib/techmap/maps/alltap.vhd
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|
Project_File_P_39 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 39 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_40 = ../../lib/techmap/maps/clkgen.vhd
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|
Project_File_P_40 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 40 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_41 = ../../lib/techmap/maps/clkmux.vhd
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|
|
Project_File_P_41 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 41 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_42 = ../../lib/techmap/maps/clkand.vhd
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|
Project_File_P_42 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 42 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_43 = ../../lib/techmap/maps/ddr_ireg.vhd
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|
|
Project_File_P_43 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 43 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_44 = ../../lib/techmap/maps/ddr_oreg.vhd
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|
|
Project_File_P_44 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 44 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_45 = ../../lib/techmap/maps/ddrphy.vhd
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|
|
Project_File_P_45 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 45 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_46 = ../../lib/techmap/maps/syncram.vhd
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|
|
Project_File_P_46 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 46 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_47 = ../../lib/techmap/maps/syncram64.vhd
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|
Project_File_P_47 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 47 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_48 = ../../lib/techmap/maps/syncram_2p.vhd
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|
Project_File_P_48 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 48 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_49 = ../../lib/techmap/maps/syncram_dp.vhd
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|
Project_File_P_49 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 49 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_50 = ../../lib/techmap/maps/syncfifo.vhd
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|
Project_File_P_50 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 50 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_51 = ../../lib/techmap/maps/regfile_3p.vhd
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|
Project_File_P_51 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 51 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_52 = ../../lib/techmap/maps/tap.vhd
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|
Project_File_P_52 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 52 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_53 = ../../lib/techmap/maps/techbuf.vhd
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|
|
Project_File_P_53 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 53 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_54 = ../../lib/techmap/maps/nandtree.vhd
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|
|
Project_File_P_54 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 54 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_55 = ../../lib/techmap/maps/clkpad.vhd
|
|
|
Project_File_P_55 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 55 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_56 = ../../lib/techmap/maps/clkpad_ds.vhd
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|
|
Project_File_P_56 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 56 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_57 = ../../lib/techmap/maps/inpad.vhd
|
|
|
Project_File_P_57 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 57 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_58 = ../../lib/techmap/maps/inpad_ds.vhd
|
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Project_File_P_58 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 58 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_59 = ../../lib/techmap/maps/iodpad.vhd
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Project_File_P_59 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 59 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_60 = ../../lib/techmap/maps/iopad.vhd
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Project_File_P_60 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 60 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_61 = ../../lib/techmap/maps/iopad_ds.vhd
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Project_File_P_61 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 61 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_62 = ../../lib/techmap/maps/lvds_combo.vhd
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Project_File_P_62 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 62 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_63 = ../../lib/techmap/maps/odpad.vhd
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Project_File_P_63 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 63 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_64 = ../../lib/techmap/maps/outpad.vhd
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Project_File_P_64 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 64 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_65 = ../../lib/techmap/maps/outpad_ds.vhd
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Project_File_P_65 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 65 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_66 = ../../lib/techmap/maps/toutpad.vhd
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Project_File_P_66 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 66 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_67 = ../../lib/techmap/maps/skew_outpad.vhd
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Project_File_P_67 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 67 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_68 = ../../lib/techmap/maps/grspwc_net.vhd
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Project_File_P_68 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 68 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_69 = ../../lib/techmap/maps/grspwc2_net.vhd
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|
Project_File_P_69 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 69 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_70 = ../../lib/techmap/maps/grlfpw_net.vhd
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|
|
Project_File_P_70 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 70 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_71 = ../../lib/techmap/maps/grfpw_net.vhd
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Project_File_P_71 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 71 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_72 = ../../lib/techmap/maps/leon4_net.vhd
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Project_File_P_72 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 72 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_73 = ../../lib/techmap/maps/mul_61x61.vhd
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|
Project_File_P_73 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 73 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_74 = ../../lib/techmap/maps/cpu_disas_net.vhd
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|
Project_File_P_74 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 74 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_75 = ../../lib/techmap/maps/grusbhc_net.vhd
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Project_File_P_75 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 75 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_76 = ../../lib/techmap/maps/ringosc.vhd
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|
Project_File_P_76 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 76 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_77 = ../../lib/techmap/maps/ssrctrl_net.vhd
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|
Project_File_P_77 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 77 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_78 = ../../lib/techmap/maps/system_monitor.vhd
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|
Project_File_P_78 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 78 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_79 = ../../lib/techmap/maps/grgates.vhd
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|
Project_File_P_79 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 79 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_80 = ../../lib/techmap/maps/inpad_ddr.vhd
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|
Project_File_P_80 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 80 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_81 = ../../lib/techmap/maps/outpad_ddr.vhd
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|
Project_File_P_81 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 81 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_82 = ../../lib/techmap/maps/iopad_ddr.vhd
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|
Project_File_P_82 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 82 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_83 = ../../lib/techmap/maps/syncram128bw.vhd
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|
Project_File_P_83 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 83 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_84 = ../../lib/techmap/maps/syncram128.vhd
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|
Project_File_P_84 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 84 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_85 = ../../lib/techmap/maps/syncram156bw.vhd
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|
Project_File_P_85 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 85 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_86 = ../../lib/techmap/maps/techmult.vhd
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|
Project_File_P_86 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 86 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_87 = ../../lib/techmap/maps/spictrl_net.vhd
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|
Project_File_P_87 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 87 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_88 = ../../lib/techmap/maps/scanreg.vhd
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|
Project_File_P_88 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to techmap compile_order 88 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_89 = ../../lib/spw/comp/spwcomp.vhd
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|
Project_File_P_89 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to spw compile_order 89 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_90 = ../../lib/spw/wrapper/grspw_gen.vhd
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|
Project_File_P_90 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to spw compile_order 90 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_91 = ../../lib/spw/wrapper/grspw2_gen.vhd
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|
Project_File_P_91 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to spw compile_order 91 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_92 = ../../lib/eth/comp/ethcomp.vhd
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|
Project_File_P_92 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 92 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_93 = ../../lib/eth/core/greth_pkg.vhd
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|
Project_File_P_93 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 93 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_94 = ../../lib/eth/core/eth_rstgen.vhd
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|
|
Project_File_P_94 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 94 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_95 = ../../lib/eth/core/eth_edcl_ahb_mst.vhd
|
|
|
Project_File_P_95 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 95 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_96 = ../../lib/eth/core/eth_ahb_mst.vhd
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|
|
Project_File_P_96 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 96 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_97 = ../../lib/eth/core/greth_tx.vhd
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|
Project_File_P_97 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 97 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_98 = ../../lib/eth/core/greth_rx.vhd
|
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Project_File_P_98 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 98 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_99 = ../../lib/eth/core/grethc.vhd
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Project_File_P_99 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 99 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_100 = ../../lib/eth/wrapper/greth_gen.vhd
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Project_File_P_100 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 100 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_101 = ../../lib/eth/wrapper/greth_gbit_gen.vhd
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Project_File_P_101 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to eth compile_order 101 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_102 = ../../lib/opencores/occomp/occomp.vhd
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Project_File_P_102 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to opencores compile_order 102 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_103 = ../../lib/opencores/can/cancomp.vhd
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Project_File_P_103 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to opencores compile_order 103 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_104 = ../../lib/opencores/can/can_top.vhd
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Project_File_P_104 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to opencores compile_order 104 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_105 = ../../lib/gaisler/arith/arith.vhd
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Project_File_P_105 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 105 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_106 = ../../lib/gaisler/arith/mul32.vhd
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Project_File_P_106 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 106 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_107 = ../../lib/gaisler/arith/div32.vhd
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Project_File_P_107 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 107 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_108 = ../../lib/gaisler/memctrl/memctrl.vhd
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Project_File_P_108 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 108 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_109 = ../../lib/gaisler/memctrl/sdctrl.vhd
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Project_File_P_109 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 109 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_110 = ../../lib/gaisler/memctrl/sdctrl64.vhd
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Project_File_P_110 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 110 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_111 = ../../lib/gaisler/memctrl/sdmctrl.vhd
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Project_File_P_111 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 111 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_112 = ../../lib/gaisler/memctrl/srctrl.vhd
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Project_File_P_112 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 112 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_113 = ../../lib/gaisler/memctrl/spimctrl.vhd
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Project_File_P_113 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 113 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_114 = ../../lib/gaisler/leon3/leon3.vhd
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Project_File_P_114 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 114 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_115 = ../../lib/gaisler/leon3/mmuconfig.vhd
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Project_File_P_115 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 115 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_116 = ../../lib/gaisler/leon3/mmuiface.vhd
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Project_File_P_116 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 116 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_117 = ../../lib/gaisler/leon3/libmmu.vhd
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Project_File_P_117 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 117 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_118 = ../../lib/gaisler/leon3/libiu.vhd
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Project_File_P_118 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 118 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_119 = ../../lib/gaisler/leon3/libcache.vhd
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Project_File_P_119 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 119 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_120 = ../../lib/gaisler/leon3/libproc3.vhd
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Project_File_P_120 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 120 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_121 = ../../lib/gaisler/leon3/cachemem.vhd
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Project_File_P_121 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 121 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_122 = ../../lib/gaisler/leon3/mmu_icache.vhd
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Project_File_P_122 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 122 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_123 = ../../lib/gaisler/leon3/mmu_dcache.vhd
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Project_File_P_123 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 123 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_124 = ../../lib/gaisler/leon3/mmu_acache.vhd
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|
Project_File_P_124 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 124 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_125 = ../../lib/gaisler/leon3/mmutlbcam.vhd
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|
Project_File_P_125 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 125 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_126 = ../../lib/gaisler/leon3/mmulrue.vhd
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|
Project_File_P_126 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 126 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_127 = ../../lib/gaisler/leon3/mmulru.vhd
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|
Project_File_P_127 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 127 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_128 = ../../lib/gaisler/leon3/mmutlb.vhd
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|
Project_File_P_128 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 128 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_129 = ../../lib/gaisler/leon3/mmutw.vhd
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|
Project_File_P_129 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 129 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_130 = ../../lib/gaisler/leon3/mmu.vhd
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|
Project_File_P_130 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 130 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_131 = ../../lib/gaisler/leon3/mmu_cache.vhd
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|
Project_File_P_131 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 131 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_132 = ../../lib/gaisler/leon3/cpu_disasx.vhd
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|
Project_File_P_132 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 132 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_133 = ../../lib/gaisler/leon3/iu3.vhd
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|
|
Project_File_P_133 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 133 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
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Project_File_134 = ../../lib/gaisler/leon3/grfpwx.vhd
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|
|
Project_File_P_134 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 134 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_135 = ../../lib/gaisler/leon3/mfpwx.vhd
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|
|
Project_File_P_135 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 135 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_136 = ../../lib/gaisler/leon3/grlfpwx.vhd
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|
|
Project_File_P_136 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 136 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_137 = ../../lib/gaisler/leon3/tbufmem.vhd
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|
Project_File_P_137 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 137 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_138 = ../../lib/gaisler/leon3/dsu3x.vhd
|
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Project_File_P_138 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 138 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_139 = ../../lib/gaisler/leon3/dsu3.vhd
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Project_File_P_139 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 139 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_140 = ../../lib/gaisler/leon3/proc3.vhd
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Project_File_P_140 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 140 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_141 = ../../lib/gaisler/leon3/leon3s.vhd
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Project_File_P_141 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 141 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_142 = ../../lib/gaisler/leon3/leon3cg.vhd
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Project_File_P_142 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 142 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_143 = ../../lib/gaisler/leon3/irqmp.vhd
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Project_File_P_143 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 143 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_144 = ../../lib/gaisler/leon3/grfpwxsh.vhd
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Project_File_P_144 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 144 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_145 = ../../lib/gaisler/leon3/grfpushwx.vhd
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Project_File_P_145 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 145 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_146 = ../../lib/gaisler/leon3/leon3sh.vhd
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Project_File_P_146 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 146 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_147 = ../../lib/gaisler/leon3ft/leon3ft.vhd
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Project_File_P_147 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 147 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_148 = ../../lib/gaisler/can/can.vhd
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Project_File_P_148 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 148 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_149 = ../../lib/gaisler/can/can_mod.vhd
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|
Project_File_P_149 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 149 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_150 = ../../lib/gaisler/can/can_oc.vhd
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|
Project_File_P_150 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 150 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_151 = ../../lib/gaisler/can/can_mc.vhd
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Project_File_P_151 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 151 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_152 = ../../lib/gaisler/can/canmux.vhd
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|
Project_File_P_152 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 152 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_153 = ../../lib/gaisler/can/can_rd.vhd
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|
Project_File_P_153 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 153 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_154 = ../../lib/gaisler/misc/misc.vhd
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Project_File_P_154 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 154 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_155 = ../../lib/gaisler/misc/rstgen.vhd
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|
Project_File_P_155 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 155 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_156 = ../../lib/gaisler/misc/gptimer.vhd
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|
Project_File_P_156 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 156 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_157 = ../../lib/gaisler/misc/ahbram.vhd
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|
|
Project_File_P_157 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 157 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_158 = ../../lib/gaisler/misc/ahbdpram.vhd
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|
Project_File_P_158 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 158 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_159 = ../../lib/gaisler/misc/ahbtrace.vhd
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|
|
Project_File_P_159 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 159 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_160 = ../../lib/gaisler/misc/ahbtrace_mb.vhd
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|
|
Project_File_P_160 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 160 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_161 = ../../lib/gaisler/misc/ahbtrace_mmb.vhd
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|
|
Project_File_P_161 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 161 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_162 = ../../lib/gaisler/misc/ahbmst.vhd
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|
Project_File_P_162 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 162 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_163 = ../../lib/gaisler/misc/grgpio.vhd
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|
Project_File_P_163 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 163 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_164 = ../../lib/gaisler/misc/ahbstat.vhd
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|
Project_File_P_164 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 164 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_165 = ../../lib/gaisler/misc/logan.vhd
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|
Project_File_P_165 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 165 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_166 = ../../lib/gaisler/misc/apbps2.vhd
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|
Project_File_P_166 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 166 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_167 = ../../lib/gaisler/misc/charrom_package.vhd
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|
|
Project_File_P_167 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 167 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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|
Project_File_168 = ../../lib/gaisler/misc/charrom.vhd
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|
Project_File_P_168 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 168 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_169 = ../../lib/gaisler/misc/apbvga.vhd
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|
Project_File_P_169 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 169 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_170 = ../../lib/gaisler/misc/svgactrl.vhd
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|
Project_File_P_170 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 170 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_171 = ../../lib/gaisler/misc/i2cmst_gen.vhd
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|
Project_File_P_171 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 171 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_172 = ../../lib/gaisler/misc/spictrlx.vhd
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|
|
Project_File_P_172 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 172 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_173 = ../../lib/gaisler/misc/spictrl.vhd
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|
|
Project_File_P_173 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 173 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
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Project_File_174 = ../../lib/gaisler/misc/i2cslv.vhd
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|
|
Project_File_P_174 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 174 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_175 = ../../lib/gaisler/misc/wild.vhd
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|
Project_File_P_175 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 175 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_176 = ../../lib/gaisler/misc/wild2ahb.vhd
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|
Project_File_P_176 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 176 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_177 = ../../lib/gaisler/misc/grsysmon.vhd
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|
Project_File_P_177 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 177 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_178 = ../../lib/gaisler/misc/gracectrl.vhd
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Project_File_P_178 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 178 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_179 = ../../lib/gaisler/misc/grgpreg.vhd
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Project_File_P_179 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 179 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_180 = ../../lib/gaisler/misc/ahbmst2.vhd
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Project_File_P_180 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 180 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_181 = ../../lib/gaisler/misc/ahb_mst_iface.vhd
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Project_File_P_181 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 181 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_182 = ../../lib/gaisler/ambatest/ahbtbp.vhd
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Project_File_P_182 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 182 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_183 = ../../lib/gaisler/ambatest/ahbtbm.vhd
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Project_File_P_183 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 183 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_184 = ../../lib/gaisler/net/net.vhd
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Project_File_P_184 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 184 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_185 = ../../lib/gaisler/uart/uart.vhd
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Project_File_P_185 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 185 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_186 = ../../lib/gaisler/uart/libdcom.vhd
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Project_File_P_186 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 186 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_187 = ../../lib/gaisler/uart/apbuart.vhd
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Project_File_P_187 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 187 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_188 = ../../lib/gaisler/uart/dcom.vhd
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Project_File_P_188 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 188 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_189 = ../../lib/gaisler/uart/dcom_uart.vhd
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|
Project_File_P_189 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 189 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_190 = ../../lib/gaisler/uart/ahbuart.vhd
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Project_File_P_190 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 190 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_191 = ../../lib/gaisler/sim/i2c_slave_model.v
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Project_File_P_191 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 compile_to gaisler vlog_upper 0 vlog_options {} compile_order 191 dont_compile 0
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Project_File_192 = ../../lib/gaisler/sim/sim.vhd
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|
Project_File_P_192 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 192 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_193 = ../../lib/gaisler/sim/sram.vhd
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|
Project_File_P_193 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 193 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_194 = ../../lib/gaisler/sim/ata_device.vhd
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|
Project_File_P_194 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 194 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_195 = ../../lib/gaisler/sim/sram16.vhd
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|
Project_File_P_195 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 195 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_196 = ../../lib/gaisler/sim/phy.vhd
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|
Project_File_P_196 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 196 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_197 = ../../lib/gaisler/sim/ahbrep.vhd
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|
Project_File_P_197 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 197 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_198 = ../../lib/gaisler/sim/delay_wire.vhd
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|
Project_File_P_198 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 198 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_199 = ../../lib/gaisler/sim/spi_flash.vhd
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|
|
Project_File_P_199 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 199 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_200 = ../../lib/gaisler/sim/pwm_check.vhd
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|
|
Project_File_P_200 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 200 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
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Project_File_201 = ../../lib/gaisler/sim/usbsim.vhd
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|
|
Project_File_P_201 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 201 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_202 = ../../lib/gaisler/sim/grusbdcsim.vhd
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|
|
Project_File_P_202 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 202 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_203 = ../../lib/gaisler/sim/grusb_dclsim.vhd
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|
|
Project_File_P_203 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 203 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_204 = ../../lib/gaisler/jtag/jtag.vhd
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|
|
Project_File_P_204 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 204 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_205 = ../../lib/gaisler/jtag/libjtagcom.vhd
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|
|
Project_File_P_205 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 205 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_206 = ../../lib/gaisler/jtag/jtagcom.vhd
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|
|
Project_File_P_206 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 206 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
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Project_File_207 = ../../lib/gaisler/jtag/ahbjtag.vhd
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|
|
Project_File_P_207 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 207 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
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Project_File_208 = ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
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|
|
Project_File_P_208 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 208 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
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Project_File_209 = ../../lib/gaisler/jtag/bscanregs.vhd
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|
|
Project_File_P_209 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 209 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_210 = ../../lib/gaisler/jtag/bscanregsbd.vhd
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|
|
Project_File_P_210 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 210 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_211 = ../../lib/gaisler/jtag/jtagtst.vhd
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|
|
Project_File_P_211 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 211 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_212 = ../../lib/gaisler/greth/ethernet_mac.vhd
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|
|
Project_File_P_212 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 212 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_213 = ../../lib/gaisler/greth/greth.vhd
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|
|
Project_File_P_213 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 213 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_214 = ../../lib/gaisler/greth/greth_mb.vhd
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|
|
Project_File_P_214 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 214 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_215 = ../../lib/gaisler/greth/greth_gbit.vhd
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|
|
Project_File_P_215 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 215 dont_compile 0 cover_stmt 1 vhdl_use93 93
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|
|
Project_File_216 = ../../lib/gaisler/greth/greth_gbit_mb.vhd
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|
|
Project_File_P_216 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 216 dont_compile 0 cover_stmt 1 vhdl_use93 93
|
|
|
Project_File_217 = ../../lib/gaisler/greth/grethm.vhd
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|
|
Project_File_P_217 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 217 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_218 = ../../lib/gaisler/spacewire/spacewire.vhd
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Project_File_P_218 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 218 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_219 = ../../lib/gaisler/spacewire/grspw.vhd
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Project_File_P_219 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 219 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_220 = ../../lib/gaisler/spacewire/grspw2.vhd
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Project_File_P_220 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 220 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_221 = ../../lib/gaisler/spacewire/grspwm.vhd
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Project_File_P_221 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 221 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_222 = ../../lib/gaisler/gr1553b/gr1553b_pkg.vhd
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Project_File_P_222 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gaisler compile_order 222 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_223 = ../../lib/esa/memoryctrl/memoryctrl.vhd
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Project_File_P_223 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to esa compile_order 223 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_224 = ../../lib/esa/memoryctrl/mctrl.vhd
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Project_File_P_224 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to esa compile_order 224 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_225 = ../../lib/fmf/utilities/conversions.vhd
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Project_File_P_225 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 225 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_226 = ../../lib/fmf/utilities/gen_utils.vhd
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Project_File_P_226 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 226 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_227 = ../../lib/fmf/flash/flash.vhd
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Project_File_P_227 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 227 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_228 = ../../lib/fmf/flash/s25fl064a.vhd
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Project_File_P_228 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 228 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_229 = ../../lib/fmf/flash/m25p80.vhd
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Project_File_P_229 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 229 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_230 = ../../lib/fmf/fifo/idt7202.vhd
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Project_File_P_230 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to fmf compile_order 230 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_231 = ../../lib/gsi/ssram/functions.vhd
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Project_File_P_231 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gsi compile_order 231 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_232 = ../../lib/gsi/ssram/core_burst.vhd
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Project_File_P_232 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gsi compile_order 232 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_233 = ../../lib/gsi/ssram/g880e18bt.vhd
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Project_File_P_233 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to gsi compile_order 233 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_234 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
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Project_File_P_234 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 234 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_235 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
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Project_File_P_235 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 235 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_236 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
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Project_File_P_236 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 236 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_237 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
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Project_File_P_237 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 237 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_238 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
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Project_File_P_238 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 238 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_239 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
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Project_File_P_239 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 239 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_240 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
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|
Project_File_P_240 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 240 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_241 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
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Project_File_P_241 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 241 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_242 = ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
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Project_File_P_242 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 242 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_243 = ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
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|
Project_File_P_243 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 243 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_244 = ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
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Project_File_P_244 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 244 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_245 = ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
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Project_File_P_245 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 245 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_246 = ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
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Project_File_P_246 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 246 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_247 = ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
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Project_File_P_247 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 247 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_248 = ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
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Project_File_P_248 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 248 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_249 = ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
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Project_File_P_249 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 249 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_250 = ../../lib/lpp/./dsp/iir_filter/RAM.vhd
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Project_File_P_250 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 250 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_251 = ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
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|
Project_File_P_251 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 251 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_252 = ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
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|
Project_File_P_252 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 252 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_253 = ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
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|
Project_File_P_253 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 253 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_254 = ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
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Project_File_P_254 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 254 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_255 = ../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd
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|
Project_File_P_255 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 255 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_256 = ../../lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd
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|
Project_File_P_256 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 256 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_257 = ../../lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
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Project_File_P_257 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 257 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_258 = ../../lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
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Project_File_P_258 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 258 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_259 = ../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd
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Project_File_P_259 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 259 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_260 = ../../lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
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Project_File_P_260 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 260 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_261 = ../../lib/lpp/./dsp/lpp_fft/actar.vhd
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Project_File_P_261 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 261 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_262 = ../../lib/lpp/./dsp/lpp_fft/actram.vhd
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Project_File_P_262 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 262 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_263 = ../../lib/lpp/./dsp/lpp_fft/fftDp.vhd
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Project_File_P_263 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 263 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_264 = ../../lib/lpp/./dsp/lpp_fft/fftSm.vhd
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Project_File_P_264 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 264 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_265 = ../../lib/lpp/./dsp/lpp_fft/fft_components.vhd
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Project_File_P_265 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 265 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_266 = ../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
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Project_File_P_266 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 266 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_267 = ../../lib/lpp/./dsp/lpp_fft/primitives.vhd
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Project_File_P_267 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 267 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_268 = ../../lib/lpp/./dsp/lpp_fft/twiddle.vhd
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Project_File_P_268 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 268 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_269 = ../../lib/lpp/./general_purpose/ADDRcntr.vhd
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Project_File_P_269 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 269 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_270 = ../../lib/lpp/./general_purpose/ALU.vhd
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Project_File_P_270 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 270 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_271 = ../../lib/lpp/./general_purpose/Adder.vhd
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Project_File_P_271 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 271 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_272 = ../../lib/lpp/./general_purpose/Clk_divider.vhd
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Project_File_P_272 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 272 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_273 = ../../lib/lpp/./general_purpose/MAC.vhd
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Project_File_P_273 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 273 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_274 = ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
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Project_File_P_274 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 274 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_275 = ../../lib/lpp/./general_purpose/MAC_MUX.vhd
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Project_File_P_275 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 275 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_276 = ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
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Project_File_P_276 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 276 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_277 = ../../lib/lpp/./general_purpose/MAC_REG.vhd
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Project_File_P_277 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 277 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_278 = ../../lib/lpp/./general_purpose/MUX2.vhd
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Project_File_P_278 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 278 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_279 = ../../lib/lpp/./general_purpose/Multiplier.vhd
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Project_File_P_279 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 279 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_280 = ../../lib/lpp/./general_purpose/REG.vhd
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Project_File_P_280 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 280 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_281 = ../../lib/lpp/./general_purpose/Shifter.vhd
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Project_File_P_281 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 281 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_282 = ../../lib/lpp/./general_purpose/general_purpose.vhd
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Project_File_P_282 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 282 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_283 = ../../lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd
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Project_File_P_283 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 283 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_284 = ../../lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd
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Project_File_P_284 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 284 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_285 = ../../lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd
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Project_File_P_285 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 285 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_286 = ../../lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd
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Project_File_P_286 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 286 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_287 = ../../lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd
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Project_File_P_287 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 287 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_288 = ../../lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd
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Project_File_P_288 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 288 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_289 = ../../lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd
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Project_File_P_289 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 289 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_290 = ../../lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd
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Project_File_P_290 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 290 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_291 = ../../lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd
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|
Project_File_P_291 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 291 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_292 = ../../lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd
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|
Project_File_P_292 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 292 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_293 = ../../lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd
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Project_File_P_293 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 293 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_294 = ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
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|
Project_File_P_294 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 294 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_295 = ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
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|
Project_File_P_295 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 295 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_296 = ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
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Project_File_P_296 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 296 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_297 = ../../lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd
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Project_File_P_297 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 297 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_298 = ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
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Project_File_P_298 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 298 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_299 = ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
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Project_File_P_299 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 299 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_300 = ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
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Project_File_P_300 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 300 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_301 = ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
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Project_File_P_301 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 301 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_302 = ../../lib/lpp/./lpp_amba/apb_devices_list.vhd
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Project_File_P_302 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 302 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_303 = ../../lib/lpp/./lpp_amba/lpp_amba.vhd
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Project_File_P_303 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 303 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_304 = ../../lib/lpp/./lpp_cna/APB_CNA.vhd
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Project_File_P_304 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 304 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_305 = ../../lib/lpp/./lpp_cna/CNA_TabloC.vhd
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Project_File_P_305 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 305 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_306 = ../../lib/lpp/./lpp_cna/Convertisseur_config.vhd
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Project_File_P_306 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 306 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_307 = ../../lib/lpp/./lpp_cna/Gene_SYNC.vhd
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Project_File_P_307 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 307 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_308 = ../../lib/lpp/./lpp_cna/Serialize.vhd
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Project_File_P_308 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 308 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_309 = ../../lib/lpp/./lpp_cna/Systeme_Clock.vhd
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|
Project_File_P_309 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 309 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_310 = ../../lib/lpp/./lpp_cna/lpp_cna.vhd
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Project_File_P_310 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 310 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_311 = ../../lib/lpp/./lpp_matrix/ALU_Driver.vhd
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Project_File_P_311 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 311 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_312 = ../../lib/lpp/./lpp_matrix/ALU_v2.vhd
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Project_File_P_312 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 312 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_313 = ../../lib/lpp/./lpp_matrix/APB_Matrix.vhd
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Project_File_P_313 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 313 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_314 = ../../lib/lpp/./lpp_matrix/DriveInputs.vhd
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Project_File_P_314 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 314 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_315 = ../../lib/lpp/./lpp_matrix/GetResult.vhd
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Project_File_P_315 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 315 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_316 = ../../lib/lpp/./lpp_matrix/MAC_v2.vhd
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Project_File_P_316 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 316 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_317 = ../../lib/lpp/./lpp_matrix/Matrix.vhd
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Project_File_P_317 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 317 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_318 = ../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd
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Project_File_P_318 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 318 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_319 = ../../lib/lpp/./lpp_matrix/Starter.vhd
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Project_File_P_319 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 319 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_320 = ../../lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd
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|
Project_File_P_320 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 320 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_321 = ../../lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd
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|
Project_File_P_321 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 321 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_322 = ../../lib/lpp/./lpp_matrix/TwoComplementer.vhd
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|
Project_File_P_322 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 322 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_323 = ../../lib/lpp/./lpp_matrix/lpp_matrix.vhd
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|
Project_File_P_323 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 323 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_324 = ../../lib/lpp/./lpp_memory/APB_FIFO.vhd
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|
Project_File_P_324 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 324 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_325 = ../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd
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|
Project_File_P_325 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 325 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_326 = ../../lib/lpp/./lpp_memory/lppFIFOx5.vhd
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|
Project_File_P_326 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 326 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_327 = ../../lib/lpp/./lpp_memory/lpp_FIFO.vhd
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|
Project_File_P_327 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 327 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_328 = ../../lib/lpp/./lpp_memory/lpp_memory.vhd
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|
Project_File_P_328 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 328 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_329 = ../../lib/lpp/./lpp_uart/APB_UART.vhd
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|
Project_File_P_329 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 329 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_330 = ../../lib/lpp/./lpp_uart/BaudGen.vhd
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|
Project_File_P_330 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 330 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_331 = ../../lib/lpp/./lpp_uart/Shift_REG.vhd
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|
|
Project_File_P_331 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 331 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_332 = ../../lib/lpp/./lpp_uart/UART.vhd
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|
Project_File_P_332 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 332 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_333 = ../../lib/lpp/./lpp_uart/lpp_uart.vhd
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|
|
Project_File_P_333 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 333 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_334 = ../../lib/lpp/./lpp_usb/APB_USB.vhd
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|
Project_File_P_334 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 334 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_335 = ../../lib/lpp/./lpp_usb/RWbuf.vhd
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Project_File_P_335 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 335 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_336 = ../../lib/lpp/./lpp_usb/lpp_usb.vhd
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Project_File_P_336 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to lpp compile_order 336 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_337 = ../../lib/cypress/ssram/components.vhd
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Project_File_P_337 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to cypress compile_order 337 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_338 = ../../lib/cypress/ssram/package_utility.vhd
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Project_File_P_338 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to cypress compile_order 338 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_339 = ../../lib/cypress/ssram/cy7c1354b.vhd
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Project_File_P_339 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to cypress compile_order 339 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_340 = ../../lib/cypress/ssram/cy7c1380d.vhd
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Project_File_P_340 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to cypress compile_order 340 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_341 = ../../lib/work/debug/debug.vhd
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Project_File_P_341 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 341 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_342 = ../../lib/work/debug/grtestmod.vhd
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Project_File_P_342 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 342 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_343 = ../../lib/work/debug/cpu_disas.vhd
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Project_File_P_343 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 343 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_344 = config.vhd
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Project_File_P_344 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 344 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_345 = ahbrom.vhd
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Project_File_P_345 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 345 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_File_346 = leon3mp.vhd
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Project_File_P_346 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to work compile_order 346 dont_compile 0 cover_stmt 1 vhdl_use93 93
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Project_Sim_Count = 1
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Project_Sim_0 = Simulation 1
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Project_Sim_P_0 = Generics {} timing default -std_output {} +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} +acc {} ok 1 folder {Top Level} -absentisempty 0 +pulse_r {} OtherArgs {} -multisource_delay {} +pulse_e {} -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t ps additional_dus work.testbench -nofileshare 0 -noglitch 0 -wlf {} +no_pulse_msg 0 -assertfile {} -sdfnowarn 0 -Lf {} -std_input {}
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Project_Folder_Count = 0
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Echo_Compile_Output = 0
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Save_Compile_Report = 1
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VHDL_DoubleClick = Edit
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VERILOG_DoubleClick = Edit
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SYSTEMC_DoubleClick = Edit
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TCL_DoubleClick = Edit
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TEXT_DoubleClick = Edit
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VHDL_CustomDoubleClick =
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VERILOG_CustomDoubleClick =
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SYSTEMC_CustomDoubleClick =
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TCL_CustomDoubleClick =
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TEXT_CustomDoubleClick =
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ForceSoftPaths = 0
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