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[Library]
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grlib = modelsim/grlib
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proasic3 = modelsim/proasic3
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synplify = modelsim/synplify
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techmap = modelsim/techmap
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spw = modelsim/spw
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eth = modelsim/eth
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opencores = modelsim/opencores
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gaisler = modelsim/gaisler
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esa = modelsim/esa
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fmf = modelsim/fmf
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spansion = modelsim/spansion
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gsi = modelsim/gsi
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lpp = modelsim/lpp
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cypress = modelsim/cypress
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work = modelsim/work
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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vital2000 = $MODEL_TECH/../vital2000
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verilog = $MODEL_TECH/../verilog
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arithmetic = $MODEL_TECH/../arithmetic
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mgc_portable = $MODEL_TECH/../mgc_portable
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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[vcom]
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; Turn on VHDL-1993 as the default. Normally is off.
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VHDL93 = 1
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; Show source line containing error. Default is off.
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Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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Explicit = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = false
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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; NoVital = 1
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; Turn off inclusion of debugging info within design units. Default is to include.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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[vlog]
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; Turn off inclusion of debugging info within design units. Default is to include.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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[vsim]
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; vopt flow
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; Set to turn on automatic optimization of a design.
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; Default is off (pre-6.0 flow without vopt).
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VoptFlow = 0
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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Resolution = 1ps
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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UserTimeUnit = ns
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; Default run length
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RunLength = 100
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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; Directive to license manager:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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; nomgc Do not look for Mentor Graphics Licenses
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; nomti Do not look for Model Technology Licenses
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; noqueue Do not wait in the license queue when a license isn't available
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; License = plus
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; Stop the simulator after an assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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BreakOnAssertion = 3
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; Assertion Message Format
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; %S - Severity Level
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; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
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; %I - Instance or Region pathname (if available)
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; %% - print '%' character
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; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; Default radix for all windows and commands...
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = symbolic
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; VSIM Startup command
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; Startup = do startup.do
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; File for saving command transcript
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TranscriptFile = transcript
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; Specify whether paths in simulator commands should be described
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; in VHDL or Verilog format. For VHDL, PathSeparator = /
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; for Verilog, PathSeparator = .
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PathSeparator = /
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; Disable assertion messages
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; IgnoreNote = 1
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; IgnoreWarning = 1
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; IgnoreError = 1
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; IgnoreFailure = 1
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; Default force kind. May be freeze, drive, or deposit
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; or in other terms, fixed, wired or charged.
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; DefaultForceKind = freeze
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; If zero, open files when elaborated
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; else open files on first read or write
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; DelayFileOpen = 0
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; Control VHDL files opened for write
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; 0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
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; This controls the number of characters of a signal name
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; shown in the waveform window and the postscript plot.
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; The default value or a value of zero tells VSIM to display
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; the full name.
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; WaveSignalNameWidth = 10
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; Turn off warnings from the std_logic_arith, std_logic_unsigned
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; and std_logic_signed packages.
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StdArithNoWarnings = 1
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; Turn off warnings from the IEEE numeric_std and numeric_bit
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; packages.
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NumericStdNoWarnings = 1
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; Control the format of a generate statement label. Don't quote it.
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; GenerateFormat = %s__%d
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; Specify whether checkpoint files should be compressed.
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; The default is to be compressed.
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
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; Veriuser = veriuser.sl
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[lmc]
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
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libsm = $MODEL_TECH/libsm.sl
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
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; libsm = $MODEL_TECH/libsm.dll
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; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
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; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
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; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
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; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
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; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
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; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
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; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
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; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
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; and run "vsim.swift".
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; Logic Modeling's SmartModel SWIFT software (Windows NT)
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; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
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; ModelSim's interface to Logic Modeling's hardware modeler SFI software
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libhm = $MODEL_TECH/libhm.sl
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; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
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; libhm = $MODEL_TECH/libhm.dll
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; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
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; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
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; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
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; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
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; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
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; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
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; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
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; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
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; Logic Modeling's hardware modeler SFI software (Window NT)
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; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
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