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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL; -- PLE
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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ENTITY leon3ft_soc IS
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GENERIC (
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fabtech : INTEGER := apa3e;
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memtech : INTEGER := apa3e;
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padtech : INTEGER := inferred;
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clktech : INTEGER := inferred;
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disas : INTEGER := 0; -- Enable disassembly to console
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dbguart : INTEGER := 0; -- Print UART on console
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pclow : INTEGER := 2;
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--
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clk_freq : INTEGER := 25000; --kHz
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--
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NB_CPU : INTEGER := 1;
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ENABLE_FPU : INTEGER := 1;
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FPU_NETLIST : INTEGER := 1;
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ENABLE_DSU : INTEGER := 1;
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ENABLE_AHB_UART : INTEGER := 1;
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ENABLE_APB_UART : INTEGER := 1;
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ENABLE_IRQMP : INTEGER := 1;
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ENABLE_GPT : INTEGER := 1;
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--
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NB_AHB_MASTER : INTEGER := 11;
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NB_AHB_SLAVE : INTEGER := 1;
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NB_APB_SLAVE : INTEGER := 2
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);
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PORT (
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clk : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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errorn : OUT STD_ULOGIC;
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-- UART AHB ---------------------------------------------------------------
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ahbrxd : IN STD_ULOGIC; -- DSU rx data
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ahbtxd : OUT STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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urxd1 : IN STD_ULOGIC; -- UART1 rx data
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utxd1 : OUT STD_ULOGIC; -- UART1 tx data
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-- RAM --------------------------------------------------------------------
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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-- APB --------------------------------------------------------------------
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apbi_ext : OUT apb_slv_in_type;
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apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
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-- AHB_Slave --------------------------------------------------------------
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ahbi_s_ext : OUT ahb_slv_in_type;
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ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
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-- AHB_Master -------------------------------------------------------------
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ahbi_m_ext : OUT AHB_Mst_In_Type;
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ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
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);
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END;
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ARCHITECTURE Behavioral OF leon3ft_soc IS
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-----------------------------------------------------------------------------
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-- CONFIG -------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Clock generator
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CONSTANT CFG_CLKMUL : INTEGER := (1);
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CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
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CONSTANT CFG_OCLKDIV : INTEGER := (1);
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CONSTANT CFG_CLK_NOFB : INTEGER := 0;
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-- LEON3 processor core
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CONSTANT CFG_LEON3 : INTEGER := 1;
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CONSTANT CFG_NCPU : INTEGER := NB_CPU;
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CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
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CONSTANT CFG_V8 : INTEGER := 0;
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CONSTANT CFG_MAC : INTEGER := 0;
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CONSTANT CFG_SVT : INTEGER := 0;
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CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
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CONSTANT CFG_LDDEL : INTEGER := (1);
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CONSTANT CFG_NWP : INTEGER := (0);
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CONSTANT CFG_PWD : INTEGER := 1*2;
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CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
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-- 1*(8 + 16 * 0) => grfpu-light
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-- 1*(8 + 16 * 1) => netlist
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-- 0*(8 + 16 * 0) => No FPU
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-- 0*(8 + 16 * 1) => No FPU;
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CONSTANT CFG_ICEN : INTEGER := 1;
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CONSTANT CFG_ISETS : INTEGER := 1;
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CONSTANT CFG_ISETSZ : INTEGER := 4;
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CONSTANT CFG_ILINE : INTEGER := 4;
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CONSTANT CFG_IREPL : INTEGER := 0;
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CONSTANT CFG_ILOCK : INTEGER := 0;
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CONSTANT CFG_ILRAMEN : INTEGER := 0;
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CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
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CONSTANT CFG_ILRAMSZ : INTEGER := 1;
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CONSTANT CFG_DCEN : INTEGER := 1;
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CONSTANT CFG_DSETS : INTEGER := 1;
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CONSTANT CFG_DSETSZ : INTEGER := 4;
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CONSTANT CFG_DLINE : INTEGER := 4;
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CONSTANT CFG_DREPL : INTEGER := 0;
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CONSTANT CFG_DLOCK : INTEGER := 0;
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CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
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CONSTANT CFG_DLRAMEN : INTEGER := 0;
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CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
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CONSTANT CFG_DLRAMSZ : INTEGER := 1;
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CONSTANT CFG_MMUEN : INTEGER := 0;
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CONSTANT CFG_ITLBNUM : INTEGER := 2;
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CONSTANT CFG_DTLBNUM : INTEGER := 2;
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CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
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CONSTANT CFG_TLB_REP : INTEGER := 1;
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CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
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CONSTANT CFG_ITBSZ : INTEGER := 0;
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CONSTANT CFG_ATBSZ : INTEGER := 0;
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-- AMBA settings
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CONSTANT CFG_DEFMST : INTEGER := (0);
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CONSTANT CFG_RROBIN : INTEGER := 1;
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CONSTANT CFG_SPLIT : INTEGER := 0;
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CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
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CONSTANT CFG_APBADDR : INTEGER := 16#800#;
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-- DSU UART
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CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
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-- LEON2 memory controller
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CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
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-- UART 1
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CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
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CONSTANT CFG_UART1_FIFO : INTEGER := 1;
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-- LEON3 interrupt controller
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CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
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-- Modular timer
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CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
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CONSTANT CFG_GPT_NTIM : INTEGER := (2);
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CONSTANT CFG_GPT_SW : INTEGER := (8);
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CONSTANT CFG_GPT_TW : INTEGER := (32);
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CONSTANT CFG_GPT_IRQ : INTEGER := (8);
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CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
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CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
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CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SIGNALs
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-----------------------------------------------------------------------------
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CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
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-- CLK & RST --
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SIGNAL clk2x : STD_ULOGIC;
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SIGNAL clkmn : STD_ULOGIC;
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SIGNAL clkm : STD_ULOGIC;
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SIGNAL rstn : STD_ULOGIC;
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SIGNAL rstraw : STD_ULOGIC;
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SIGNAL pciclk : STD_ULOGIC;
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SIGNAL sdclkl : STD_ULOGIC;
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SIGNAL cgi : clkgen_in_type;
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SIGNAL cgo : clkgen_out_type;
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--- AHB / APB
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
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SIGNAL ahbsi : ahb_slv_in_type;
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SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
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SIGNAL ahbmi : ahb_mst_in_type;
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SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
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--UART
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SIGNAL ahbuarti : uart_in_type;
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SIGNAL ahbuarto : uart_out_type;
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SIGNAL apbuarti : uart_in_type;
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SIGNAL apbuarto : uart_out_type;
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--MEM CTRLR
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SIGNAL memi : memory_in_type;
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SIGNAL memo : memory_out_type;
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SIGNAL wpo : wprot_out_type;
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SIGNAL sdo : sdram_out_type;
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--IRQ
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SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
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SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
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--Timer
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SIGNAL gpti : gptimer_in_type;
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SIGNAL gpto : gptimer_out_type;
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--DSU
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SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
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SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
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SIGNAL dsui : dsu_in_type;
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SIGNAL dsuo : dsu_out_type;
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-----------------------------------------------------------------------------
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SIGNAL nSRAM_CE_s : STD_LOGIC;
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BEGIN
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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cgi.pllctrl <= "00";
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cgi.pllrst <= rstraw;
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rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
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clkgen0 : clkgen -- clock generator
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GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
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PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
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----------------------------------------------------------------------
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--- LEON3 processor / DSU / IRQ ------------------------------------
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----------------------------------------------------------------------
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l3 : IF CFG_LEON3 = 1 GENERATE
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cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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u0 : leon3ft
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GENERIC MAP (
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hindex => i, --: integer;
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fabtech => fabtech,
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memtech => memtech,
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nwindows => CFG_NWIN,
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dsu => CFG_DSU,
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fpu => CFG_FPU,
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v8 => CFG_V8,
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cp => 0,
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mac => CFG_MAC,
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pclow => pclow,
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notag => 0,
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nwp => CFG_NWP,
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icen => CFG_ICEN,
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irepl => CFG_IREPL,
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isets => CFG_ISETS,
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ilinesize => CFG_ILINE,
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isetsize => CFG_ISETSZ,
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isetlock => CFG_ILOCK,
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dcen => CFG_DCEN,
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drepl => CFG_DREPL,
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dsets => CFG_DSETS,
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dlinesize => CFG_DLINE,
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dsetsize => CFG_DSETSZ,
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dsetlock => CFG_DLOCK,
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dsnoop => CFG_DSNOOP,
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ilram => CFG_ILRAMEN,
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ilramsize => CFG_ILRAMSZ,
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ilramstart => CFG_ILRAMADDR,
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dlram => CFG_DLRAMEN,
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dlramsize => CFG_DLRAMSZ,
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dlramstart => CFG_DLRAMADDR,
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mmuen => CFG_MMUEN,
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itlbnum => CFG_ITLBNUM,
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dtlbnum => CFG_DTLBNUM,
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tlb_type => CFG_TLB_TYPE,
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tlb_rep => CFG_TLB_REP,
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lddel => CFG_LDDEL,
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disas => disas,
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tbuf => CFG_ITBSZ,
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pwd => CFG_PWD,
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svt => CFG_SVT,
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rstaddr => CFG_RSTADDR,
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smp => CFG_NCPU-1,
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iuft => 2, --: integer range 0 to 4;
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fpft => 1, --: integer range 0 to 4;
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cmft => 1, --: integer range 0 to 1;
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iuinj => 0, --: integer;
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ceinj => 0, --: integer range 0 to 3;
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cached => 0, --: integer;
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netlist => 0, --: integer;
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scantest => 0, --: integer;
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mmupgsz => 0, --: integer range 0 to 5;
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bp => 1) --: integer);
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PORT MAP (
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clk => clkm,
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rstn => rstn,
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ahbi => ahbmi,
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ahbo => ahbmo(i),
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ahbsi => ahbsi,
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ahbso => ahbso,
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irqi => irqi(i),
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irqo => irqo(i),
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dbgi => dbgi(i),
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dbgo => dbgo(i),
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gclk => clkm
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);
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END GENERATE;
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errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
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dsugen : IF CFG_DSU = 1 GENERATE
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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dsui.break <= '0';
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END GENERATE;
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END GENERATE;
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nodsu : IF CFG_DSU = 0 GENERATE
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ahbso(2) <= ahbs_none;
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dsuo.tstop <= '0';
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dsuo.active <= '0';
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END GENERATE;
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irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
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irqctrl0 : irqmp -- interrupt controller
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GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
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END GENERATE;
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irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
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x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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irqi(i).irl <= "0000";
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END GENERATE;
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apbo(2) <= apb_none;
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END GENERATE;
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----------------------------------------------------------------------
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--- Memory controllers ---------------------------------------------
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----------------------------------------------------------------------
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memctrlr : mctrl GENERIC MAP (
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hindex => 0,
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pindex => 0,
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paddr => 0,
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srbanks => 1
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)
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PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
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memi.brdyn <= '1';
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memi.bexcn <= '1';
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memi.writen <= '1';
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memi.wrn <= "1111";
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memi.bwidth <= "10";
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bdr : FOR i IN 0 TO 3 GENERATE
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data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
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PORT MAP (
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data(31-i*8 DOWNTO 24-i*8),
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memo.data(31-i*8 DOWNTO 24-i*8),
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memo.bdrive(i),
|
|
|
memi.data(31-i*8 DOWNTO 24-i*8));
|
|
|
END GENERATE;
|
|
|
|
|
|
addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
|
|
|
PORT MAP (address, memo.address(21 DOWNTO 2));
|
|
|
nSRAM_CE_s <= NOT(memo.ramsn(0));
|
|
|
rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
|
|
|
oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
|
|
|
nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
|
|
|
nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
|
|
|
nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
|
|
|
nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
|
|
|
nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB CONTROLLER -------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
ahb0 : ahbctrl -- AHB arbiter/multiplexer
|
|
|
GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
|
|
|
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
|
|
|
ioen => 0, nahbm => maxahbmsp, nahbs => 8)
|
|
|
PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
dcomgen : IF CFG_AHB_UART = 1 GENERATE
|
|
|
dcom0 : ahbuart
|
|
|
GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
|
|
|
PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
|
|
|
dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
|
|
|
dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
|
|
|
END GENERATE;
|
|
|
nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB Bridge -----------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
apb0 : apbctrl -- AHB/APB bridge
|
|
|
GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
|
|
|
PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- GPT Timer ------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
|
|
|
timer0 : gptimer -- timer unit
|
|
|
GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
|
|
nbits => CFG_GPT_TW)
|
|
|
PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
|
|
|
gpti.dhalt <= dsuo.tstop;
|
|
|
gpti.extclk <= '0';
|
|
|
END GENERATE;
|
|
|
notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
|
|
|
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
|
|
|
uart1 : apbuart -- UART 1
|
|
|
GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
|
|
|
apbuarti.rxd <= urxd1;
|
|
|
apbuarti.extclk <= '0';
|
|
|
utxd1 <= apbuarto.txd;
|
|
|
apbuarti.ctsn <= '0';
|
|
|
END GENERATE;
|
|
|
noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- AMBA BUS -------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
-- APB --------------------------------------------------------------------
|
|
|
apbi_ext <= apbi;
|
|
|
all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
|
|
|
max_16_apb : IF I + 5 < 16 GENERATE
|
|
|
apbo(I+5) <= apbo_ext(I+5);
|
|
|
END GENERATE max_16_apb;
|
|
|
END GENERATE all_apb;
|
|
|
-- AHB_Slave --------------------------------------------------------------
|
|
|
ahbi_s_ext <= ahbsi;
|
|
|
all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
|
|
|
max_16_ahbs : IF I + 3 < 16 GENERATE
|
|
|
ahbso(I+3) <= ahbo_s_ext(I+3);
|
|
|
END GENERATE max_16_ahbs;
|
|
|
END GENERATE all_ahbs;
|
|
|
-- AHB_Master -------------------------------------------------------------
|
|
|
ahbi_m_ext <= ahbmi;
|
|
|
all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
|
|
|
max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
|
|
|
ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
|
|
|
END GENERATE max_16_ahbm;
|
|
|
END GENERATE all_ahbm;
|
|
|
|
|
|
|
|
|
|
|
|
END Behavioral;
|
|
|
|