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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.data_type_pkg.ALL;
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ENTITY sig_reader IS
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GENERIC(
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FNAME : STRING := "input.txt";
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WIDTH : INTEGER := 1;
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RESOLUTION : INTEGER := 8;
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GAIN : REAL := 1.0
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);
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PORT(
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clk : IN std_logic;
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end_of_simu : out std_logic;
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out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
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);
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END sig_reader;
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ARCHITECTURE beh OF sig_reader IS
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FILE input_file : TEXT OPEN read_mode IS FNAME;
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SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
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SIGNAL end_of_simu_reg : std_logic:='0';
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BEGIN
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out_signal <= out_signal_reg;
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end_of_simu <= end_of_simu_reg;
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PROCESS
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VARIABLE line_var : LINE;
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VARIABLE value : INTEGER;
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VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
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BEGIN
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WAIT UNTIL clk = '1';
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IF endfile(input_file) THEN
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end_of_simu_reg <= '1';
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ELSE
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end_of_simu_reg <= '0';
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readline(input_file,line_var);
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FOR COL IN 0 TO WIDTH-1 LOOP
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read(line_var, value);
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cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
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FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
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out_signal_reg(COL,bit_idx) <= cell(bit_idx);
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END LOOP;
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END LOOP;
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END IF;
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END PROCESS;
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END beh;
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