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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL; -- PLE
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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USE work.config.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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ENTITY leon3mp IS
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GENERIC (
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fabtech : INTEGER := CFG_FABTECH;
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memtech : INTEGER := CFG_MEMTECH;
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padtech : INTEGER := CFG_PADTECH;
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clktech : INTEGER := CFG_CLKTECH;
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disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
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dbguart : INTEGER := CFG_DUART; -- Print UART on console
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pclow : INTEGER := CFG_PCLOW
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);
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PORT (
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clk100MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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errorn : OUT STD_ULOGIC;
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-- UART AHB ---------------------------------------------------------------
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ahbrxd : IN STD_ULOGIC; -- DSU rx data
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ahbtxd : OUT STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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urxd1 : IN STD_ULOGIC; -- UART1 rx data
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utxd1 : OUT STD_ULOGIC; -- UART1 tx data
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-- RAM --------------------------------------------------------------------
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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-- SPW --------------------------------------------------------------------
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spw1_din : IN STD_LOGIC; -- PLE
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spw1_sin : IN STD_LOGIC; -- PLE
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spw1_dout : OUT STD_LOGIC; -- PLE
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spw1_sout : OUT STD_LOGIC; -- PLE
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spw2_din : IN STD_LOGIC; -- JCPE --TODO
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spw2_sin : IN STD_LOGIC; -- JCPE --TODO
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spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
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spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
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-- ADC --------------------------------------------------------------------
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bias_fail_sw : OUT STD_LOGIC;
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ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ADC_smpclk : OUT STD_LOGIC;
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ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
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---------------------------------------------------------------------------
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led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
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);
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END;
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ARCHITECTURE Behavioral OF leon3mp IS
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--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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-- CFG_GRETH+CFG_AHB_JTAG;
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CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
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CFG_AHB_UART
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+2;
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-- 1 is for the SpaceWire module grspw, which is a master
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-- 1 is for the LFR
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CONSTANT maxahbm : INTEGER := maxahbmsp;
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--Clk & Rst g�n�
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SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL resetnl : STD_ULOGIC;
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SIGNAL clk2x : STD_ULOGIC;
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SIGNAL lclk2x : STD_ULOGIC;
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SIGNAL lclk25MHz : STD_ULOGIC;
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SIGNAL lclk50MHz : STD_ULOGIC;
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SIGNAL lclk100MHz : STD_ULOGIC;
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SIGNAL clkm : STD_ULOGIC;
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SIGNAL rstn : STD_ULOGIC;
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SIGNAL rstraw : STD_ULOGIC;
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SIGNAL pciclk : STD_ULOGIC;
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SIGNAL sdclkl : STD_ULOGIC;
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SIGNAL cgi : clkgen_in_type;
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SIGNAL cgo : clkgen_out_type;
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--- AHB / APB
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
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SIGNAL ahbsi : ahb_slv_in_type;
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SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
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SIGNAL ahbmi : ahb_mst_in_type;
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SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
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--UART
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SIGNAL ahbuarti : uart_in_type;
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SIGNAL ahbuarto : uart_out_type;
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SIGNAL apbuarti : uart_in_type;
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SIGNAL apbuarto : uart_out_type;
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--MEM CTRLR
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SIGNAL memi : memory_in_type;
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SIGNAL memo : memory_out_type;
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SIGNAL wpo : wprot_out_type;
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SIGNAL sdo : sdram_out_type;
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SIGNAL ramcs : STD_ULOGIC;
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--IRQ
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SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
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SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
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--Timer
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SIGNAL gpti : gptimer_in_type;
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SIGNAL gpto : gptimer_out_type;
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--GPIO
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SIGNAL gpioi : gpio_in_type;
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SIGNAL gpioo : gpio_out_type;
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--DSU
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SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
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SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
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SIGNAL dsui : dsu_in_type;
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SIGNAL dsuo : dsu_out_type;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------Signaux----------------------
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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CONSTANT IOAEN : INTEGER := CFG_CAN;
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CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
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-- time management signal
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-- Spacewire signals
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SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
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SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
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SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
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SIGNAL spw_rxtxclk : STD_ULOGIC;
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SIGNAL spw_rxclkn : STD_ULOGIC;
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SIGNAL spw_clk : STD_LOGIC;
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SIGNAL swni : grspw_in_type; -- PLE
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SIGNAL swno : grspw_out_type; -- PLE
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SIGNAL clkmn : STD_ULOGIC; -- PLE
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SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
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-- AD Converter RHF1401
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SIGNAL sample : Samples14v(7 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
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BEGIN
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
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clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
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clkgen0 : clkgen -- clock generator
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GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
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PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
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PROCESS(lclk100MHz)
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BEGIN
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IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
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lclk50MHz <= NOT lclk50MHz;
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END IF;
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END PROCESS;
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PROCESS(lclk50MHz)
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BEGIN
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IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
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lclk25MHz <= NOT lclk25MHz;
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END IF;
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END PROCESS;
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lclk2x <= lclk50MHz;
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spw_clk <= lclk50MHz;
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----------------------------------------------------------------------
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--- LEON3 processor / DSU / IRQ ------------------------------------
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----------------------------------------------------------------------
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l3 : IF CFG_LEON3 = 1 GENERATE
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cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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u0 : leon3s -- LEON3 processor
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GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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END GENERATE;
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errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
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dsugen : IF CFG_DSU = 1 GENERATE
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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dsui.break <= '0';
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led(2) <= dsuo.active;
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END GENERATE;
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END GENERATE;
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nodsu : IF CFG_DSU = 0 GENERATE
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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END GENERATE;
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irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
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irqctrl0 : irqmp -- interrupt controller
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GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
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END GENERATE;
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irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
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x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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irqi(i).irl <= "0000";
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END GENERATE;
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apbo(2) <= apb_none;
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END GENERATE;
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----------------------------------------------------------------------
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--- Memory controllers ---------------------------------------------
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----------------------------------------------------------------------
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memctrlr : mctrl GENERIC MAP (
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hindex => 0,
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pindex => 0,
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paddr => 0,
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srbanks => 1
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)
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PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
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memi.brdyn <= '1';
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memi.bexcn <= '1';
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memi.writen <= '1';
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memi.wrn <= "1111";
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memi.bwidth <= "10";
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bdr : FOR i IN 0 TO 3 GENERATE
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data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
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PORT MAP (
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data(31-i*8 DOWNTO 24-i*8),
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memo.data(31-i*8 DOWNTO 24-i*8),
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memo.bdrive(i),
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memi.data(31-i*8 DOWNTO 24-i*8));
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END GENERATE;
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addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
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PORT MAP (address, memo.address(21 DOWNTO 2));
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rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
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oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
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nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
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nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
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nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
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nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
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nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
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----------------------------------------------------------------------
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--- AHB CONTROLLER -------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- AHB UART -------------------------------------------------------
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----------------------------------------------------------------------
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dcomgen : IF CFG_AHB_UART = 1 GENERATE
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dcom0 : ahbuart
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GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
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PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
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dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
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dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
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led(0) <= NOT ahbuarti.rxd;
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led(1) <= NOT ahbuarto.txd;
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END GENERATE;
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nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
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----------------------------------------------------------------------
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--- APB Bridge -----------------------------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
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PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
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----------------------------------------------------------------------
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--- GPT Timer ------------------------------------------------------
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----------------------------------------------------------------------
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gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
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timer0 : gptimer -- timer unit
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GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
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sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
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nbits => CFG_GPT_TW)
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PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
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gpti.dhalt <= dsuo.tstop;
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gpti.extclk <= '0';
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END GENERATE;
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notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
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----------------------------------------------------------------------
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--- APB UART -------------------------------------------------------
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----------------------------------------------------------------------
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ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
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|
|
uart1 : apbuart -- UART 1
|
|
|
GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
|
|
|
apbuarti.rxd <= urxd1;
|
|
|
apbuarti.extclk <= '0';
|
|
|
utxd1 <= apbuarto.txd;
|
|
|
apbuarti.ctsn <= '0';
|
|
|
END GENERATE;
|
|
|
noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
|
|
apb_lfr_time_management_1: apb_lfr_time_management
|
|
|
GENERIC MAP (
|
|
|
pindex => 6,
|
|
|
paddr => 6,
|
|
|
pmask => 16#fff#,
|
|
|
pirq => 12)
|
|
|
PORT MAP (
|
|
|
clk25MHz => clkm,
|
|
|
clk49_152MHz => clk49_152MHz,
|
|
|
resetn => rstn,
|
|
|
grspw_tick => swno.tickout,
|
|
|
apbi => apbi,
|
|
|
apbo => apbo(6),
|
|
|
coarse_time => coarse_time,
|
|
|
fine_time => fine_time);
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- SpaceWire --------------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
spw_rxtxclk <= spw_clk;
|
|
|
spw_rxclkn <= NOT spw_rxtxclk;
|
|
|
|
|
|
-- PADS for SPW1
|
|
|
spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw1_din, dtmp(0));
|
|
|
spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw1_sin, stmp(0));
|
|
|
spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw1_dout, swno.d(0));
|
|
|
spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw1_sout, swno.s(0));
|
|
|
-- PADS FOR SPW2
|
|
|
spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw2_din, dtmp(1));
|
|
|
spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw2_sin, stmp(1));
|
|
|
spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw2_dout, swno.d(1));
|
|
|
spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
|
|
|
PORT MAP (spw2_sout, swno.s(1));
|
|
|
|
|
|
-- GRSPW PHY
|
|
|
--spw1_input: if CFG_SPW_GRSPW = 1 generate
|
|
|
spw_inputloop : FOR j IN 0 TO 1 GENERATE
|
|
|
spw_phy0 : grspw_phy
|
|
|
GENERIC MAP(
|
|
|
tech => fabtech,
|
|
|
rxclkbuftype => 1,
|
|
|
scantest => 0)
|
|
|
PORT MAP(
|
|
|
rxrst => swno.rxrst,
|
|
|
di => dtmp(j),
|
|
|
si => stmp(j),
|
|
|
rxclko => spw_rxclk(j),
|
|
|
do => swni.d(j),
|
|
|
ndo => swni.nd(j*5+4 DOWNTO j*5),
|
|
|
dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
|
|
|
END GENERATE spw_inputloop;
|
|
|
|
|
|
-- SPW core
|
|
|
sw0 : grspwm
|
|
|
GENERIC MAP(
|
|
|
tech => apa3e,
|
|
|
hindex => 1,
|
|
|
pindex => 5,
|
|
|
paddr => 5,
|
|
|
pirq => 11,
|
|
|
sysfreq => 25000, -- CPU_FREQ
|
|
|
rmap => 1,
|
|
|
rmapcrc => 1,
|
|
|
fifosize1 => 16,
|
|
|
fifosize2 => 16,
|
|
|
rxclkbuftype => 1,
|
|
|
rxunaligned => 0,
|
|
|
rmapbufs => 4,
|
|
|
ft => 0,
|
|
|
netlist => 0,
|
|
|
ports => 2,
|
|
|
--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
|
|
|
memtech => apa3e,
|
|
|
destkey => 2,
|
|
|
spwcore => 1
|
|
|
--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
|
|
|
--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
|
|
|
--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
|
|
|
)
|
|
|
PORT MAP(rstn, clkm, spw_rxclk(0),
|
|
|
spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
|
|
|
ahbmi, ahbmo(1), apbi, apbo(5),
|
|
|
swni, swno);
|
|
|
|
|
|
swni.tickin <= '0';
|
|
|
swni.rmapen <= '1';
|
|
|
swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
|
|
|
swni.tickinraw <= '0';
|
|
|
swni.timein <= (OTHERS => '0');
|
|
|
swni.dcrstval <= (OTHERS => '0');
|
|
|
swni.timerrstval <= (OTHERS => '0');
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- LFR
|
|
|
-------------------------------------------------------------------------------
|
|
|
lpp_lfr_1 : lpp_lfr
|
|
|
GENERIC MAP (
|
|
|
Mem_use => use_RAM,
|
|
|
nb_data_by_buffer_size => 32,
|
|
|
nb_word_by_buffer_size => 30,
|
|
|
nb_snapshot_param_size => 32,
|
|
|
delta_vector_size => 32,
|
|
|
delta_vector_size_f0_2 => 7, -- log2(96)
|
|
|
pindex => 15,
|
|
|
paddr => 15,
|
|
|
pmask => 16#fff#,
|
|
|
pirq_ms => 6,
|
|
|
pirq_wfp => 14,
|
|
|
hindex => 2,
|
|
|
top_lfr_version => X"00000002")
|
|
|
PORT MAP (
|
|
|
clk => clkm,
|
|
|
rstn => rstn,
|
|
|
sample_B => sample(2 DOWNTO 0),
|
|
|
sample_E => sample(7 DOWNTO 3),
|
|
|
sample_val => sample_val,
|
|
|
apbi => apbi,
|
|
|
apbo => apbo(15),
|
|
|
ahbi => ahbmi,
|
|
|
ahbo => ahbmo(2),
|
|
|
coarse_time => coarse_time,
|
|
|
fine_time => fine_time,
|
|
|
data_shaping_BW => bias_fail_sw);
|
|
|
|
|
|
top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 8,
|
|
|
ncycle_cnv_high => 79,
|
|
|
ncycle_cnv => 500)
|
|
|
PORT MAP (
|
|
|
cnv_clk => clk49_152MHz,
|
|
|
cnv_rstn => rstn,
|
|
|
cnv => ADC_smpclk,
|
|
|
clk => clkm,
|
|
|
rstn => rstn,
|
|
|
ADC_data => ADC_data,
|
|
|
ADC_nOE => ADC_OEB_bar_CH,
|
|
|
sample => sample,
|
|
|
sample_val => sample_val);
|
|
|
|
|
|
END Behavioral;
|
|
|
|
