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This leon3 design is tailored to the Xilinx SP605 Spartan6 board
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Simulation and synthesis
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------------------------
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The design uses the Xilinx MIG memory interface with an AHB-2.0
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interface. The MIG source code cannot be distributed due to the
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prohibitive Xilinx license, so the MIG must be re-generated with
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coregen before simulation and synthesis can be done.
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To generate the MIG and install tne Xilinx unisim simulation
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library, do as follows:
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make mig
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make install-secureip
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This will ONLY work with ISE-13.2 installed, and the XILINX variable
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properly set in the shell. To synthesize the design, do
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make ise
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and then
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make ise-prog-fpga
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to program the FPGA.
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Design specifics
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----------------
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* System reset is mapped to the CPU RESET button
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* The AHB and processor is clocked by a 60 MHz clock, generated
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from the 33 MHz SYSACE clock using a DCM. You can change the frequency
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generation in the clocks menu of xconfig. The DDR3 (MIG) controller
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runs at 667 MHz.
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* The GRETH core is enabled and runs without problems at 100 Mbit.
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Ethernet debug link is enabled and has IP 192.168.0.51.
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1 Gbit operation is also possible (requires grlib com release),
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uncomment related timing constraints in the leon3mp.ucf first.
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* 16-bit flash prom can be read at address 0. It can be programmed
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with GRMON version 1.1.16 or later.
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* DDR3 is working with the provided Xilinx MIG DDR3 controller.
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If you want to simulate this design, first install the secure
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IP models with:
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make install-secureip
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Then rebuild the scripts and simulation model:
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make distclean vsim
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Modelsim v6.6e or newer is required to build the secure IP models.
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Note that the regular leon3 test bench cannot be run in simulation
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as the DDR3 model lacks data pre-load.
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* The application UART1 is connected to the USB/UART connector
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* The SVGA frame buffer uses a separate port on the DDR3 controller,
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and therefore does not noticeably affect the performance of the processor.
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Default output is analog VGA, to switch to DVI mode execute this
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command in grmon:
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i2c dvi init_l4itx_vga
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* The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
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Start grmon with -xilusb to connect.
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* Output from GRMON is:
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$ grmon -xilusb -u
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GRMON LEON debug monitor v1.1.51 professional version (debug)
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Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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Xilinx cable: Cable type/rev : 0x3
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JTAG chain: xc6slx45t xccace
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GRLIB build version: 4111
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initialising ...............
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detected frequency: 50 MHz
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SRAM waitstates: 1
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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GR Ethernet MAC Gaisler Research
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LEON2 Memory Controller European Space Agency
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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Xilinx MIG DDR2 controller Gaisler Research
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AHB/APB Bridge Gaisler Research
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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SVGA Controller Gaisler Research
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AMBA Wrapper for OC I2C-master Gaisler Research
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General purpose I/O port Gaisler Research
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AHB status register Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> inf sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
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ahb master 1
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02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
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ahb master 2, irq 12
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apb: 80000e00 - 80000f00
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Device index: dev0
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edcl ip 192.168.1.51, buffer 2 kbyte
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00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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apb: 80000000 - 80000100
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16-bit prom @ 0x00000000
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
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CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
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icache 2 * 8 kbyte, 32 byte/line rnd
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dcache 2 * 4 kbyte, 16 byte/line rnd
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04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
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ahb: 40000000 - 48000000
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apb: 80100000 - 80100100
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DDR2: 128 Mbyte
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0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80100000 - 80200000
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38343, DSU mode (FIFO debug)
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 50
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06.01:063 Gaisler Research SVGA Controller (ver 0x0)
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apb: 80000600 - 80000700
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clk0: 50.00 MHz
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09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
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irq 14
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apb: 80000900 - 80000a00
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0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
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apb: 80000a00 - 80000b00
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0f.01:052 Gaisler Research AHB status register (ver 0x0)
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irq 7
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apb: 80000f00 - 80001000
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grlib> fla
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Intel-style 16-bit flash on D[31:16]
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Manuf. Intel
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Device Strataflash P30
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Device ID 02e44603e127ffff
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User ID ffffffffffffffff
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1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
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CFI info
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flash family : 1
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flash size : 256 Mbit
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erase regions : 2
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erase blocks : 259
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write buffer : 1024 bytes
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lock-down : yes
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region 0 : 255 blocks of 128 Kbytes
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region 1 : 4 blocks of 32 Kbytes
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grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
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section: .text at 0x40000000, size 102544 bytes
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section: .data at 0x40019090, size 2788 bytes
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total size: 105332 bytes (1.2 Mbit/s)
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read 272 symbols
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entry point: 0x40000000
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grlib> run
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2K performance run parameters for coremark.
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CoreMark Size : 666
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Total ticks : 19945918
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Total time (secs): 19.945918
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Iterations/Sec : 100.271143
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Iterations : 2000
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Compiler version : GCC4.4.2
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Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
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Memory location : STACK
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seedcrc : 0xe9f5
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[0]crclist : 0xe714
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[0]crcmatrix : 0x1fd7
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[0]crcstate : 0x8e3a
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[0]crcfinal : 0x4983
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Correct operation validated. See readme.txt for run and reporting rules.
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CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
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Program exited normally.
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grlib>
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