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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY lpp_lfr_ms_reg_head IS
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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in_wen : IN STD_LOGIC;
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in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
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in_full : IN STD_LOGIC;
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in_empty : IN STD_LOGIC;
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out_write_error : OUT STD_LOGIC;
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out_wen : OUT STD_LOGIC;
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out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
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out_full : OUT STD_LOGIC
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);
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END lpp_lfr_ms_reg_head;
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ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
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TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
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SIGNAL fsm_state : fsm_state_reg_head;
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SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
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SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
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SIGNAL out_wen_s : STD_LOGIC;
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SIGNAL in_full_s : STD_LOGIC;
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BEGIN -- Beh
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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fsm_state <= REG_EMPTY;
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reg_data <= (OTHERS => '0');
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reg_data2 <= (OTHERS => '0');
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out_wen_s <= '1';
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out_write_error <= '0';
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in_full_s <= '0';
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ELSIF clk'event AND clk = '1' THEN
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in_full_s <= in_full;
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out_wen_s <= '1';
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out_write_error <= '0';
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CASE fsm_state IS
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WHEN REG_EMPTY =>
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reg_data <= in_data;
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IF in_wen = '0' AND in_full_s = '1' THEN
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fsm_state <= REG_ONE_DATA;
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END IF;
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WHEN REG_ONE_DATA =>
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reg_data2 <= in_data;
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IF in_wen = '0' AND in_full_s = '1' THEN
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fsm_state <= REG_FULL;
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ELSIF in_empty = '1' THEN
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out_wen_s <= '0';
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IF in_wen = '0' THEN
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reg_data <= in_data;
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ELSE
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fsm_state <= REG_EMPTY;
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END IF;
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END IF;
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WHEN REG_FULL =>
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IF in_empty = '1' THEN
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out_wen_s <= '0';
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IF in_wen = '0' THEN
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reg_data2 <= in_data;
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ELSE
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fsm_state <= REG_FULL_2;
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END IF;
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ELSE
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IF in_wen = '0' THEN
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out_write_error <= '1';
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END IF;
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END IF;
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WHEN REG_FULL_2 =>
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out_wen_s <= '0';
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fsm_state <= REG_EMPTY;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s;
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out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
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reg_data WHEN fsm_state = REG_ONE_DATA ELSE
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reg_data WHEN fsm_state = REG_FULL_2 ELSE
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in_data;
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out_wen <= '0' WHEN out_wen_s = '0' ELSE
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'1' WHEN fsm_state = REG_ONE_DATA ELSE
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'1' WHEN fsm_state = REG_FULL ELSE
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'1' WHEN in_full_s = '1' ELSE
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in_wen;
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END Beh;
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