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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library lpp;
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use lpp.lpp_amba.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_cna is
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component APB_CNA is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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SYNC : out std_logic;
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SCLK : out std_logic;
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DATA : out std_logic
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);
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end component;
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component CNA_TabloC is
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port(
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clock : in std_logic;
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rst : in std_logic;
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flag_nw : in std_logic;
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bp : in std_logic;
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Data_C : in std_logic_vector(15 downto 0);
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SYNC : out std_logic;
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SCLK : out std_logic;
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Rz : out std_logic;
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flag_sd : out std_logic;
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Data : out std_logic
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);
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end component;
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component Systeme_Clock is
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generic(N :integer := 695);
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port(
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clk, raz : in std_logic ;
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clock : out std_logic);
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end component;
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component Gene_SYNC is
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port(
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clk,raz : in std_logic;
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send : in std_logic;
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Sysclk : in std_logic;
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OKAI_send : out std_logic;
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SYNC : out std_logic);
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end component;
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component Serialize is
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port(
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clk,raz : in std_logic;
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sclk : in std_logic;
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vectin : in std_logic_vector(15 downto 0);
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send : in std_logic;
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sended : out std_logic;
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Data : out std_logic);
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end component;
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end;
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