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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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entity LCD_CLK_GENERATOR is
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generic(OSC_freqKHz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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clk_1us : out STD_LOGIC);
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end LCD_CLK_GENERATOR;
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architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
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Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
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signal cpt1 : integer;
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signal clk_1us_int : std_logic := '0';
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begin
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clk_1us <= clk_1us_int;
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process(reset,clk)
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begin
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if reset = '0' then
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cpt1 <= 0;
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clk_1us_int <= '0';
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elsif clk'event and clk = '1' then
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if cpt1 = clk_1usTRIGER then
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clk_1us_int <= not clk_1us_int;
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cpt1 <= 0;
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else
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cpt1 <= cpt1 + 1;
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end if;
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end if;
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end process;
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end ar_LCD_CLK_GENERATOR;
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